Re: Clarification on necessary barriers before generating IPI

Will Deacon
2020-05-20T08:29:06Z

On Wed, May 20, 2020 at 01:38:24PM +0530, Linu Cherian wrote:
> How is it ensured that system register write using msr instruction(gic_send_sgi)
> doesnt get reordered before the stores to IPI call processing
> list(call_single_queue in kernel/smp.c), so that IPI is guaranteed to
> be generated after the stores get completed.

I think the flow is:

<store to memory>
DSB ST
MSR SGI1R
ISB

and then on the receiver:

<interrupt; implicit ISB/context sync>
MRS IAR
DSB SY
<control dependency>
MSR EOIR
ISB
<handle IPI>

> CMIIW, Dont we need an isb() in addition to to the wmb() in the below code ?

There is an isb?() in the code, after the loop. Are you saying it should be
somewhere else? If so, why?

Will