Clarification on necessary barriers before generating IPI

Linu Cherian
2020-05-20T08:08:44Z

Hi,

How is it ensured that system register write using msr instruction(gic_send_sgi)
doesnt get reordered before the stores to IPI call processing
list(call_single_queue in kernel/smp.c), so that IPI is guaranteed to
be generated after the stores get completed.

CMIIW, Dont we need an isb() in addition to to the wmb() in the below code ?

Thanks.

static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
{
int cpu;

if (WARN_ON(irq >= 16))
return;

/*
* Ensure that stores to Normal memory are visible to the
* other CPUs before issuing the IPI.
*/
wmb();

for_each_cpu(cpu, mask) {
u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
u16 tlist;

tlist = gic_compute_target_list(&cpu, mask, cluster_id);
gic_send_sgi(cluster_id, tlist, irq);
}

/* Force the above writes to ICC_SGI1R_EL1 to be executed */
isb();
}