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* [arm:clearfog 9/10] drivers/pci/pcie/aspm.c:579 pcie_aspm_cap_init() warn: inconsistent indenting
@ 2020-06-04 21:58 kernel test robot
  0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2020-06-04 21:58 UTC (permalink / raw)
  To: Russell King; +Cc: kbuild-all, linux-arm-kernel

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tree:   git://git.armlinux.org.uk/~rmk/linux-arm.git clearfog
head:   8db1590173dd1c6bb6861ca938663938c1d832b8
commit: 5315e38eefb72a8444314ef491b730b99baed319 [9/10] mvebu/clearfog pcie updates
config: x86_64-randconfig-m001-20200604 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

smatch warnings:
drivers/pci/pcie/aspm.c:579 pcie_aspm_cap_init() warn: inconsistent indenting

vim +579 drivers/pci/pcie/aspm.c

   545	
   546	static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
   547	{
   548		struct pci_dev *child = link->downstream, *parent = link->pdev;
   549		struct pci_bus *linkbus = parent->subordinate;
   550		struct aspm_register_info upreg, dwreg;
   551	
   552		if (blacklist) {
   553			/* Set enabled/disable so that we will disable ASPM later */
   554			link->aspm_enabled = ASPM_STATE_ALL;
   555			link->aspm_disable = ASPM_STATE_ALL;
   556			return;
   557		}
   558	
   559		/* Get upstream/downstream components' register state */
   560		pcie_get_aspm_reg(parent, &upreg);
   561		pcie_get_aspm_reg(child, &dwreg);
   562	
   563		/*
   564		 * If ASPM not supported, don't mess with the clocks and link,
   565		 * bail out now.
   566		 */
   567		if (!(upreg.support & dwreg.support))
   568			return;
   569	
   570		/* Configure common clock before checking latencies */
   571		pcie_aspm_configure_common_clock(link);
   572	
   573		/*
   574		 * Re-read upstream/downstream components' register state
   575		 * after clock configuration
   576		 */
   577		pcie_get_aspm_reg(parent, &upreg);
   578		pcie_get_aspm_reg(child, &dwreg);
 > 579	dev_info(&parent->dev, "up support %x enabled %x\n", upreg.support, upreg.enabled);
   580	dev_info(&parent->dev, "dn support %x enabled %x\n", dwreg.support, dwreg.enabled);
   581	
   582		/*
   583		 * Setup L0s state
   584		 *
   585		 * Note that we must not enable L0s in either direction on a
   586		 * given link unless components on both sides of the link each
   587		 * support L0s.
   588		 */
   589		if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
   590			link->aspm_support |= ASPM_STATE_L0S;
   591		if (dwreg.enabled & PCIE_LINK_STATE_L0S)
   592			link->aspm_enabled |= ASPM_STATE_L0S_UP;
   593		if (upreg.enabled & PCIE_LINK_STATE_L0S)
   594			link->aspm_enabled |= ASPM_STATE_L0S_DW;
   595		link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
   596		link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
   597	
   598		/* Setup L1 state */
   599		if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
   600			link->aspm_support |= ASPM_STATE_L1;
   601		if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
   602			link->aspm_enabled |= ASPM_STATE_L1;
   603		link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
   604		link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
   605	
   606		/* Setup L1 substate */
   607		if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
   608			link->aspm_support |= ASPM_STATE_L1_1;
   609		if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
   610			link->aspm_support |= ASPM_STATE_L1_2;
   611		if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
   612			link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
   613		if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
   614			link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
   615	
   616		if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
   617			link->aspm_enabled |= ASPM_STATE_L1_1;
   618		if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
   619			link->aspm_enabled |= ASPM_STATE_L1_2;
   620		if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
   621			link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
   622		if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
   623			link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
   624	
   625		if (link->aspm_support & ASPM_STATE_L1SS)
   626			aspm_calc_l1ss_info(link, &upreg, &dwreg);
   627	
   628		/* Save default state */
   629		link->aspm_default = link->aspm_enabled;
   630	
   631		/* Setup initial capable state. Will be updated later */
   632		link->aspm_capable = link->aspm_support;
   633		/*
   634		 * If the downstream component has pci bridge function, don't
   635		 * do ASPM for now.
   636		 */
   637		list_for_each_entry(child, &linkbus->devices, bus_list) {
   638			if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
   639				link->aspm_disable = ASPM_STATE_ALL;
   640				break;
   641			}
   642		}
   643	
   644		/* Get and check endpoint acceptable latencies */
   645		list_for_each_entry(child, &linkbus->devices, bus_list) {
   646			u32 reg32, encoding;
   647			struct aspm_latency *acceptable =
   648				&link->acceptable[PCI_FUNC(child->devfn)];
   649	
   650			if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
   651			    pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
   652				continue;
   653	
   654			pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
   655			/* Calculate endpoint L0s acceptable latency */
   656			encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
   657			acceptable->l0s = calc_l0s_acceptable(encoding);
   658			/* Calculate endpoint L1 acceptable latency */
   659			encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
   660			acceptable->l1 = calc_l1_acceptable(encoding);
   661	
   662			pcie_aspm_check_latency(child);
   663		}
   664	}
   665	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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