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Mon, 8 Jun 2020 04:48:54 -0400 (EDT) Date: Mon, 8 Jun 2020 10:48:53 +0200 From: Maxime Ripard To: Samuel Holland Subject: Re: [PATCH v2 1/9] irqchip/sun6i-r: Use a stacked irqchip driver Message-ID: <20200608084853.wr6eca5nt772p5h7@gilmour.lan> References: <20200525041302.51213-1-samuel@sholland.org> <20200525041302.51213-2-samuel@sholland.org> MIME-Version: 1.0 In-Reply-To: <20200525041302.51213-2-samuel@sholland.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200608_014900_666306_CA05A287 X-CRM114-Status: GOOD ( 20.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jason Cooper , Marc Zyngier , linux-sunxi@googlegroups.com, Russell King , linux-kernel@vger.kernel.org, Chen-Yu Tsai , Rob Herring , Catalin Marinas , Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============0731134726157099507==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============0731134726157099507== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="7vhq7oykrmn4c3qk" Content-Disposition: inline --7vhq7oykrmn4c3qk Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, May 24, 2020 at 11:12:54PM -0500, Samuel Holland wrote: > The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the > original sun4i interrupt controller than the sun7i/sun9i NMI controller. > It is used for two distinct purposes: > 1) To control the trigger, latch, and mask for the NMI input pin > 2) To provide the interrupt input for the ARISC coprocessor >=20 > As this interrupt controller is not documented, information about it > comes from vendor-provided ARISC firmware and from experimentation. >=20 > Like the original sun4i interrupt controller, it has: > - A VECTOR_REG at 0x00 (configurable via the BASE_ADDR_REG at 0x04) > - A NMI_CTRL_REG, PENDING_REG, and ENABLE_REG as used by both the > sun4i and sunxi-nmi drivers > - A MASK_REG at 0x50 > - A RESP_REG at 0x60 >=20 > Differences from the sun4i interrupt controller appear to be: > - It is only known to have one register of each kind (max 32 inputs) > - There is no FIQ-related logic > - There is no interrupt priority logic >=20 > In order to fulfill its two purposes, this hardware block combines two > types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this > chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0 > pending" output from this chip, if enabled, is then routed to a SPI IRQ > input on the GIC, as IRQ_TYPE_LEVEL_HIGH. In other words, bit 0 of > ENABLE_REG *does* affect the NMI IRQ seen at the GIC. >=20 > The NMI is then followed by a contiguous block of (at least) 15 IRQ > inputs that are connected in parallel to both R_INTC and the GIC. Or > in other words, the other bits of ENABLE_REG *do not* affect the IRQs > seen at the GIC. >=20 > Finally, the global "IRQ pending" output from R_INTC, after being masked > by MASK_REG and RESP_REG, is connected to the "external interrupt" input > of the ARISC CPU (an OR1200). This path is not relevant to Linux. >=20 > Because of the 1:1 correspondence between R_INTC and GIC inputs, this is > a perfect scenario for using a stacked irqchip driver. We want to hook > into enabling/disabling IRQs to add more features to the GIC > (specifically to allow masking the NMI and setting its trigger type), > but we don't need to actually handle the IRQ in this driver. >=20 > And since R_INTC is in the always-on power domain, and its output is > connected directly in to the power management coprocessor, a stacked > irqchip driver provides a simple way to add wakeup support to this set > of IRQs. That is a future patch; for now, just the NMI is moved over. >=20 > This driver keeps the same DT binding as the existing driver. The > "interrupt" property of the R_INTC node is used to determine 1) the > offset between GIC and R_INTC hwirq numbers and 2) the type of trigger > between the R_INTC "IRQ 0 pending" output and the GIC NMI input. >=20 > This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi: > Support sun6i-a31-r-intc compatible"). >=20 > Signed-off-by: Samuel Holland As usual, thanks for that commit log (and the experiments you did to write it in the first place). Acked-by: Maxime Ripard Maxime --7vhq7oykrmn4c3qk Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHQEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXt37dQAKCRDj7w1vZxhR xfwXAPizyBvckLGns6wXiV08j4/nfH7oDaFjB/EyJghf0IUHAQDP9WOZklmQUarr ISv9usKlAe9yKa3Bpw7oyVfgim/LBQ== =B+g1 -----END PGP SIGNATURE----- --7vhq7oykrmn4c3qk-- --===============0731134726157099507== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============0731134726157099507==--