From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECD86C433E0 for ; Tue, 9 Jun 2020 17:52:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B75D6207C3 for ; Tue, 9 Jun 2020 17:52:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="M9EFcKcn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B75D6207C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=collabora.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=L/z6WNQzAUd31VY1STwv+O8rWAKm02yK9OpiO4c5vkc=; b=M9EFcKcnYerysR 3FHV0XHHc0zn2n45SMXwGB6wT0vmXiEpiDhFk+Z7KRqOHFIdHEU/Q525Y91REMNbme6jrFi+upVwg 7Hfl/XVadN6ElMkMhtH2hKCKsF/hSvuTKkDzWYbk/H6L1qNaEU+XJeq17gIRo+bC6j9taIElJXxKJ TPNUIaxqPGSWcXEh7jTda/wr4eg8h7oZc7/Z2ozeNJK7dyXCMxbM6lm+ceMCKH94r+V3uQI55Vb9d vY9JhdoA9+8bV+4o+aSd2L3HkJd/8VPUGe+rA98CXMbxr6ktxv3roUylCPB35l1Fqq3fm1dsmjKwH wDFVPZIM8HPDk7YAm4Tw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jiiQR-0003N1-MX; Tue, 09 Jun 2020 17:52:39 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jiiMb-0006Pc-Ta; Tue, 09 Jun 2020 17:48:44 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id DA6612A3BF5 From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Laurent Pinchart Subject: [PATCH v9 09/11] drm: bridge: dw-mipi-dsi: split low power cfg register into fields Date: Tue, 9 Jun 2020 20:49:57 +0300 Message-Id: <20200609174959.955926-10-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200609174959.955926-1-adrian.ratiu@collabora.com> References: <20200609174959.955926-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200609_104842_233066_2C76DB1B X-CRM114-Status: GOOD ( 11.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jernej Skrabec , Heiko Stuebner , Adrian Pop , Jonas Karlman , Philippe CORNU , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yannick FERTRE , Andrzej Hajda , linux-imx@nxp.com, kernel@collabora.com, linux-stm32@st-md-mailman.stormreply.com, Arnaud Ferraris Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org According to the Host Registers documentation for IMX, STM and RK the LP cfg register should not be written entirely in one go because some bits are reserved and should be kept to reset values, for eg. BIT(15) which is reserved in all versions. This also cleans up the code by removing the the ugly defines and making field ranges & values written more explicit. Tested-by: Adrian Pop Tested-by: Arnaud Ferraris Signed-off-by: Adrian Ratiu --- New in v6. --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 105 ++++++------------ 1 file changed, 33 insertions(+), 72 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 70df0578cbe7b..1e47d40b5becb 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -120,60 +120,6 @@ #define DSI_TO_CNT_CFG_V101 0x40 #define DSI_PCKHDL_CFG_V101 0x18 -#define MAX_RD_PKT_SIZE_LP BIT(24) -#define DCS_LW_TX_LP BIT(19) -#define DCS_SR_0P_TX_LP BIT(18) -#define DCS_SW_1P_TX_LP BIT(17) -#define DCS_SW_0P_TX_LP BIT(16) -#define GEN_LW_TX_LP BIT(14) -#define GEN_SR_2P_TX_LP BIT(13) -#define GEN_SR_1P_TX_LP BIT(12) -#define GEN_SR_0P_TX_LP BIT(11) -#define GEN_SW_2P_TX_LP BIT(10) -#define GEN_SW_1P_TX_LP BIT(9) -#define GEN_SW_0P_TX_LP BIT(8) -#define TEAR_FX_EN BIT(0) - -#define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ - DCS_LW_TX_LP | \ - DCS_SR_0P_TX_LP | \ - DCS_SW_1P_TX_LP | \ - DCS_SW_0P_TX_LP | \ - GEN_LW_TX_LP | \ - GEN_SR_2P_TX_LP | \ - GEN_SR_1P_TX_LP | \ - GEN_SR_0P_TX_LP | \ - GEN_SW_2P_TX_LP | \ - GEN_SW_1P_TX_LP | \ - GEN_SW_0P_TX_LP) - -#define EN_TEAR_FX_V101 BIT(14) -#define DCS_LW_TX_LP_V101 BIT(12) -#define GEN_LW_TX_LP_V101 BIT(11) -#define MAX_RD_PKT_SIZE_LP_V101 BIT(10) -#define DCS_SW_2P_TX_LP_V101 BIT(9) -#define DCS_SW_1P_TX_LP_V101 BIT(8) -#define DCS_SW_0P_TX_LP_V101 BIT(7) -#define GEN_SR_2P_TX_LP_V101 BIT(6) -#define GEN_SR_1P_TX_LP_V101 BIT(5) -#define GEN_SR_0P_TX_LP_V101 BIT(4) -#define GEN_SW_2P_TX_LP_V101 BIT(3) -#define GEN_SW_1P_TX_LP_V101 BIT(2) -#define GEN_SW_0P_TX_LP_V101 BIT(1) - -#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \ - GEN_LW_TX_LP_V101 | \ - MAX_RD_PKT_SIZE_LP_V101 | \ - DCS_SW_2P_TX_LP_V101 | \ - DCS_SW_1P_TX_LP_V101 | \ - DCS_SW_0P_TX_LP_V101 | \ - GEN_SR_2P_TX_LP_V101 | \ - GEN_SR_1P_TX_LP_V101 | \ - GEN_SR_0P_TX_LP_V101 | \ - GEN_SW_2P_TX_LP_V101 | \ - GEN_SW_1P_TX_LP_V101 | \ - GEN_SW_0P_TX_LP_V101) - #define DSI_GEN_HDR 0x6c #define DSI_GEN_PLD_DATA 0x70 @@ -257,7 +203,11 @@ struct dw_mipi_dsi { struct regmap_field *field_dpi_vsync_active_low; struct regmap_field *field_dpi_hsync_active_low; struct regmap_field *field_cmd_mode_ack_rqst_en; - struct regmap_field *field_cmd_mode_all_lp_en; + struct regmap_field *field_cmd_mode_gen_sw_sr_en; + struct regmap_field *field_cmd_mode_dcs_sw_sr_en; + struct regmap_field *field_cmd_mode_gen_lw_en; + struct regmap_field *field_cmd_mode_dcs_lw_en; + struct regmap_field *field_cmd_mode_max_rd_pkt_size; struct regmap_field *field_cmd_mode_en; struct regmap_field *field_cmd_pkt_status; struct regmap_field *field_vid_mode_en; @@ -315,7 +265,11 @@ struct dw_mipi_dsi_variant { struct reg_field cfg_dpi_hsync_active_low; struct reg_field cfg_cmd_mode_en; struct reg_field cfg_cmd_mode_ack_rqst_en; - struct reg_field cfg_cmd_mode_all_lp_en; + struct reg_field cfg_cmd_mode_gen_sw_sr_en; + struct reg_field cfg_cmd_mode_dcs_sw_sr_en; + struct reg_field cfg_cmd_mode_gen_lw_en; + struct reg_field cfg_cmd_mode_dcs_lw_en; + struct reg_field cfg_cmd_mode_max_rd_pkt_size; struct reg_field cfg_cmd_pkt_status; struct reg_field cfg_vid_mode_en; struct reg_field cfg_vid_mode_type; @@ -366,7 +320,11 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = { .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1), .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2), .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1), - .cfg_cmd_mode_all_lp_en = REG_FIELD(DSI_CMD_MODE_CFG, 8, 24), + .cfg_cmd_mode_gen_sw_sr_en = REG_FIELD(DSI_CMD_MODE_CFG, 8, 13), + .cfg_cmd_mode_gen_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 14, 14), + .cfg_cmd_mode_dcs_sw_sr_en = REG_FIELD(DSI_CMD_MODE_CFG, 16, 18), + .cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 19, 19), + .cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24), .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31), .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31), .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31), @@ -418,7 +376,11 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = { .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG, 6, 6), .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG, 7, 7), .cfg_cmd_mode_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 0, 0), - .cfg_cmd_mode_all_lp_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 1, 12), + .cfg_cmd_mode_gen_sw_sr_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 6), + .cfg_cmd_mode_dcs_sw_sr_en = REG_FIELD(DSI_CMD_MODE_CFG, 7, 9), + .cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 10, 10), + .cfg_cmd_mode_gen_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 11, 11), + .cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 12, 12), .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13), .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14), .cfg_vid_mode_en = REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0), @@ -554,23 +516,18 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, const struct mipi_dsi_msg *msg) { bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; - u32 cmd_mode_lp = 0; - - switch (dsi->hw_version) { - case HWVER_130: - case HWVER_131: - cmd_mode_lp = CMD_MODE_ALL_LP; - break; - case HWVER_101: - cmd_mode_lp = CMD_MODE_ALL_LP_V101; - break; - } if (msg->flags & MIPI_DSI_MSG_REQ_ACK) regmap_field_write(dsi->field_cmd_mode_ack_rqst_en, 1); - if (lpm) - regmap_field_write(dsi->field_cmd_mode_all_lp_en, cmd_mode_lp); + if (lpm) { + regmap_field_write(dsi->field_cmd_mode_gen_sw_sr_en, + ENABLE_LOW_POWER); + regmap_field_write(dsi->field_cmd_mode_dcs_sw_sr_en, 7); + regmap_field_write(dsi->field_cmd_mode_gen_lw_en, 1); + regmap_field_write(dsi->field_cmd_mode_dcs_lw_en, 1); + regmap_field_write(dsi->field_cmd_mode_max_rd_pkt_size, 1); + } regmap_field_write(dsi->field_phy_txrequestclkhs, lpm ? 0 : 1); } @@ -1256,7 +1213,11 @@ static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi) INIT_FIELD(dpi_vsync_active_low); INIT_FIELD(dpi_hsync_active_low); INIT_FIELD(cmd_mode_ack_rqst_en); - INIT_FIELD(cmd_mode_all_lp_en); + INIT_FIELD(cmd_mode_gen_sw_sr_en); + INIT_FIELD(cmd_mode_dcs_sw_sr_en); + INIT_FIELD(cmd_mode_gen_lw_en); + INIT_FIELD(cmd_mode_dcs_lw_en); + INIT_FIELD(cmd_mode_max_rd_pkt_size); INIT_FIELD(cmd_mode_en); INIT_FIELD(cmd_pkt_status); INIT_FIELD(vid_mode_en); -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel