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From: Marc Zyngier <maz@kernel.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	kvm@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com>,
	James Morse <james.morse@arm.com>,
	Andrew Scull <ascull@google.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	kvmarm@lists.cs.columbia.edu,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 01/11] KVM: arm64: Flush the instruction cache if not unmapping the VM on reboot
Date: Thu, 11 Jun 2020 10:09:46 +0100	[thread overview]
Message-ID: <20200611090956.1537104-2-maz@kernel.org> (raw)
In-Reply-To: <20200611090956.1537104-1-maz@kernel.org>

On a system with FWB, we don't need to unmap Stage-2 on reboot,
as even if userspace takes this opportunity to repaint the whole
of memory, FWB ensures that the data side stays consistent even
if the guest uses non-cacheable mappings.

However, the I-side is not necessarily coherent with the D-side
if CTR_EL0.DIC is 0. In this case, invalidate the i-cache to
preserve coherency.

Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Fixes: 892713e97ca1 ("KVM: arm64: Sidestep stage2_unmap_vm() on vcpu reset when S2FWB is supported")
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/arm.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index b0b569f2cdd0..d6988401c22a 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -989,11 +989,17 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu,
 	 * Ensure a rebooted VM will fault in RAM pages and detect if the
 	 * guest MMU is turned off and flush the caches as needed.
 	 *
-	 * S2FWB enforces all memory accesses to RAM being cacheable, we
-	 * ensure that the cache is always coherent.
+	 * S2FWB enforces all memory accesses to RAM being cacheable,
+	 * ensuring that the data side is always coherent. We still
+	 * need to invalidate the I-cache though, as FWB does *not*
+	 * imply CTR_EL0.DIC.
 	 */
-	if (vcpu->arch.has_run_once && !cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
-		stage2_unmap_vm(vcpu->kvm);
+	if (vcpu->arch.has_run_once) {
+		if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
+			stage2_unmap_vm(vcpu->kvm);
+		else
+			__flush_icache_all();
+	}
 
 	vcpu_reset_hcr(vcpu);
 
-- 
2.26.2


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  reply	other threads:[~2020-06-11  9:10 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-11  9:09 [GIT PULL] KVM/arm64 fixes for 5.8, take #1 Marc Zyngier
2020-06-11  9:09 ` Marc Zyngier [this message]
2020-06-11  9:09 ` [PATCH 02/11] KVM: arm64: Stop writing aarch32's CSSELR into ACTLR Marc Zyngier
2020-06-11  9:09 ` [PATCH 03/11] KVM: arm64: Add emulation for 32bit guests accessing ACTLR2 Marc Zyngier
2020-06-11  9:09 ` [PATCH 04/11] KVM: arm64: Stop save/restoring ACTLR_EL1 Marc Zyngier
2020-06-11  9:09 ` [PATCH 05/11] KVM: arm64: Save the host's PtrAuth keys in non-preemptible context Marc Zyngier
2020-06-11  9:09 ` [PATCH 06/11] KVM: arm64: Handle PtrAuth traps early Marc Zyngier
2020-06-11  9:09 ` [PATCH 07/11] KVM: arm64: Stop sparse from moaning at __hyp_this_cpu_ptr Marc Zyngier
2020-06-11  9:09 ` [PATCH 08/11] KVM: arm64: Remove host_cpu_context member from vcpu structure Marc Zyngier
2020-06-11  9:09 ` [PATCH 09/11] KVM: arm64: Make vcpu_cp1x() work on Big Endian hosts Marc Zyngier
2020-06-11  9:09 ` [PATCH 10/11] KVM: arm64: Synchronize sysreg state on injecting an AArch32 exception Marc Zyngier
2020-06-11  9:09 ` [PATCH 11/11] KVM: arm64: Move hyp_symbol_addr() to kvm_asm.h Marc Zyngier
2020-06-11 18:04 ` [GIT PULL] KVM/arm64 fixes for 5.8, take #1 Paolo Bonzini

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