From: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
To: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] arm64: perf: add support for Cortex-A75
Date: Fri, 19 Jun 2020 18:45:35 +0800 [thread overview]
Message-ID: <20200619184535.44835b99@xhacker.debian> (raw)
In-Reply-To: <20200619184423.5e61a838@xhacker.debian>
The Cortex-A75 uses some implementation defined perf events. This
patch sets up the necessary mapping for Cortex-A75.
Mappings are based on Cortex-A75 TRM r3p1, section C2.3 PMU Events
(pages C2-578 to C2-586).
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
---
arch/arm64/kernel/perf_event.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 743affbe0cca..55e1d75af708 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -123,6 +123,21 @@ static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
};
+static const unsigned armv8_a75_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+ PERF_CACHE_MAP_ALL_UNSUPPORTED,
+
+ [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
+ [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
+ [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
+ [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
+
+
+ [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
+ [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
+};
+
static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -940,6 +955,11 @@ static int armv8_a73_map_event(struct perf_event *event)
return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
}
+static int armv8_a75_map_event(struct perf_event *event)
+{
+ return __armv8_pmuv3_map_event(event, NULL, &armv8_a75_perf_cache_map);
+}
+
static int armv8_thunder_map_event(struct perf_event *event)
{
return __armv8_pmuv3_map_event(event, NULL,
@@ -1101,7 +1121,7 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",
- armv8_pmuv3_map_event, NULL, NULL);
+ armv8_a75_map_event, NULL, NULL);
}
static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
--
2.27.0
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next prev parent reply other threads:[~2020-06-19 10:51 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-19 10:44 [PATCH 0/3] arm64: perf: add support for Cortex-A55/A75/A76 Jisheng Zhang
2020-06-19 10:45 ` [PATCH 1/3] arm64: perf: add support for Cortex-A55 Jisheng Zhang
2020-06-19 10:45 ` Jisheng Zhang [this message]
2020-06-19 10:45 ` [PATCH 3/3] arm64: perf: add support for Cortex-A76 Jisheng Zhang
2020-07-03 12:33 ` [PATCH 0/3] arm64: perf: add support for Cortex-A55/A75/A76 Will Deacon
2020-07-06 8:04 ` Jisheng Zhang
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