From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE6CAC433E0 for ; Wed, 24 Jun 2020 11:11:29 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8D3C520823 for ; Wed, 24 Jun 2020 11:11:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Fy6UobUX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8D3C520823 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Kp/0lWYk1lkb2ZC79LiOAAqJBOcxRVIJg/jdIRtCrOM=; b=Fy6UobUXchgfYQrEyjEtUkuvi 3XKUJQwuOchCcblZxICIRmsBTSyE0y87Xjn8osrYpSUXpwPAMiIOW7Nl8L6wmKjYQxh+138QrW81G kIdQooG89W4geqokz+ergtjlFyV9t8ZZvszhrvUKOf3hsTs6w9LkAk4nyQmU6lbmNNR85A/zjcWmc EiFCWzCgBhaICff2shlQ8D+bKM2NgTfkw3VSW7WV/K+HQ2cV+xM8K298Prq8hp/XZfij8gpLEoYIW aLN+Bbkv48mQmjmD9riq0W2kvvm7xWHCw8OwVQxcZ6TBh/cPNTiobVDjjKf9/292JbDwYaO0G7+gl 8iLgXyZZA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jo3Ho-0004Db-6X; Wed, 24 Jun 2020 11:09:48 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jo3Hl-0004CY-Gk for linux-arm-kernel@lists.infradead.org; Wed, 24 Jun 2020 11:09:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 127161F1; Wed, 24 Jun 2020 04:09:45 -0700 (PDT) Received: from gaia (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BFCF53F6CF; Wed, 24 Jun 2020 04:09:43 -0700 (PDT) Date: Wed, 24 Jun 2020 12:09:33 +0100 From: Catalin Marinas To: Steven Price Subject: Re: [RFC PATCH 0/2] MTE support for KVM guest Message-ID: <20200624110904.GB11863@gaia> References: <20200617123844.29960-1-steven.price@arm.com> <20200624093846.GA11863@gaia> <20200624103412.GD25945@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Marc Zyngier , lkml - Kernel Mailing List , Dave Martin , Thomas Gleixner , Will Deacon , "kvmarm@lists.cs.columbia.edu" , arm-mail-list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 24, 2020 at 12:03:35PM +0100, Steven Price wrote: > On 24/06/2020 11:34, Dave Martin wrote: > > On Wed, Jun 24, 2020 at 10:38:48AM +0100, Catalin Marinas wrote: > > > On Tue, Jun 23, 2020 at 07:05:07PM +0100, Peter Maydell wrote: > > > > On Wed, 17 Jun 2020 at 13:39, Steven Price wrote: > > > > > These patches add support to KVM to enable MTE within a guest. It is > > > > > based on Catalin's v4 MTE user space series[1]. > > > > > > > > > > [1] http://lkml.kernel.org/r/20200515171612.1020-1-catalin.marinas%40arm.com > > > > > > > > > > Posting as an RFC as I'd like feedback on the approach taken. > > > > > > > > What's your plan for handling tags across VM migration? > > > > Will the kernel expose the tag ram to userspace so we > > > > can copy it from the source machine to the destination > > > > at the same time as we copy the actual ram contents ? > > > > > > Qemu can map the guest memory with PROT_MTE and access the tags directly > > > with LDG/STG instructions. Steven was actually asking in the cover > > > letter whether we should require that the VMM maps the guest memory with > > > PROT_MTE as a guarantee that it can access the guest tags. > > > > > > There is no architecturally visible tag ram (tag storage), that's a > > > microarchitecture detail. > > > > If userspace maps the guest memory with PROT_MTE for dump purposes, > > isn't it going to get tag check faults when accessing the memory > > (i.e., when dumping the regular memory content, not the tags > > specifically). > > > > Does it need to map two aliases, one with PROT_MTE and one without, > > and is that architecturally valid? > > Userspace would either need to have two mappings (I don't believe there are > any architectural issues with that - but this could be awkward to arrange in > some situations) or be careful to avoid faults. Basically your choices with > one mapping are: > > 1. Disable tag checking (using prctl) when touching the memory. This works > but means you lose tag checking for the VMM's own accesses during this code > sequence. > > 2. Read the tag values and ensure you use the correct tag. This suffers > from race conditions if the VM is still running. > > 3. Use one of the exceptions in the architecture that generates a Tag > Unchecked access. Sadly the only remotely useful thing I can see in the v8 > ARM is "A base register plus immediate offset addressing form, with the SP > as the base register." - but making sure SP is in range of where you want to > access would be a pain. Or: 4. Set PSTATE.TCO when accessing tagged memory in an unsafe way. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel