From: Tingwei Zhang <tingwei@codeaurora.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: tsoni@codeaurora.org,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Kim Phillips <kim.phillips@arm.com>,
Mao Jinlong <jinlmao@codeaurora.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
coresight@lists.linaro.org, Randy Dunlap <rdunlap@infradead.org>,
Mian Yousaf Kaukab <ykaukab@suse.de>,
Russell King <linux@armlinux.org.uk>,
Tingwei Zhang <tingwei@codeaurora.org>,
Leo Yan <leo.yan@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 05/21] coresight: export global symbols
Date: Wed, 1 Jul 2020 15:14:11 +0800 [thread overview]
Message-ID: <20200701071427.10477-6-tingwei@codeaurora.org> (raw)
In-Reply-To: <20200701071427.10477-1-tingwei@codeaurora.org>
From: Mian Yousaf Kaukab <ykaukab@suse.de>
Export symbols used among coresight modules.
Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 1 +
drivers/hwtracing/coresight/coresight-tmc-etr.c | 6 ++++++
drivers/hwtracing/coresight/coresight.c | 8 ++++++++
3 files changed, 15 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 84f1dcb69827..dbca77150a81 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -506,6 +506,7 @@ int etm_perf_symlink(struct coresight_device *csdev, bool link)
return 0;
}
+EXPORT_SYMBOL_GPL(etm_perf_symlink);
static ssize_t etm_perf_sink_name_show(struct device *dev,
struct device_attribute *dattr,
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 625882bc8b08..b86c76ae26b9 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -255,6 +255,7 @@ void tmc_free_sg_table(struct tmc_sg_table *sg_table)
tmc_free_table_pages(sg_table);
tmc_free_data_pages(sg_table);
}
+EXPORT_SYMBOL_GPL(tmc_free_sg_table);
/*
* Alloc pages for the table. Since this will be used by the device,
@@ -340,6 +341,7 @@ struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev,
return sg_table;
}
+EXPORT_SYMBOL_GPL(tmc_alloc_sg_table);
/*
* tmc_sg_table_sync_data_range: Sync the data buffer written
@@ -360,6 +362,7 @@ void tmc_sg_table_sync_data_range(struct tmc_sg_table *table,
PAGE_SIZE, DMA_FROM_DEVICE);
}
}
+EXPORT_SYMBOL_GPL(tmc_sg_table_sync_data_range);
/* tmc_sg_sync_table: Sync the page table */
void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table)
@@ -372,6 +375,7 @@ void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table)
dma_sync_single_for_device(real_dev, table_pages->daddrs[i],
PAGE_SIZE, DMA_TO_DEVICE);
}
+EXPORT_SYMBOL_GPL(tmc_sg_table_sync_table);
/*
* tmc_sg_table_get_data: Get the buffer pointer for data @offset
@@ -401,6 +405,7 @@ ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table,
*bufpp = page_address(data_pages->pages[pg_idx]) + pg_offset;
return len;
}
+EXPORT_SYMBOL_GPL(tmc_sg_table_get_data);
#ifdef ETR_SG_DEBUG
/* Map a dma address to virtual address */
@@ -766,6 +771,7 @@ tmc_etr_get_catu_device(struct tmc_drvdata *drvdata)
return NULL;
}
+EXPORT_SYMBOL_GPL(tmc_etr_get_catu_device);
static inline int tmc_etr_enable_catu(struct tmc_drvdata *drvdata,
struct etr_buf *etr_buf)
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index e057c991df6f..e8c4e10b75b5 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -55,6 +55,7 @@ static struct list_head *stm_path;
*/
const u32 coresight_barrier_pkt[4] = {
0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff};
+EXPORT_SYMBOL_GPL(coresight_barrier_pkt);
static int coresight_id_match(struct device *dev, void *data)
{
@@ -180,6 +181,7 @@ int coresight_claim_device_unlocked(void __iomem *base)
coresight_clear_claim_tags(base);
return -EBUSY;
}
+EXPORT_SYMBOL_GPL(coresight_claim_device_unlocked);
int coresight_claim_device(void __iomem *base)
{
@@ -191,6 +193,7 @@ int coresight_claim_device(void __iomem *base)
return rc;
}
+EXPORT_SYMBOL_GPL(coresight_claim_device);
/*
* coresight_disclaim_device_unlocked : Clear the claim tags for the device.
@@ -209,6 +212,7 @@ void coresight_disclaim_device_unlocked(void __iomem *base)
*/
WARN_ON_ONCE(1);
}
+EXPORT_SYMBOL_GPL(coresight_disclaim_device_unlocked);
void coresight_disclaim_device(void __iomem *base)
{
@@ -216,6 +220,7 @@ void coresight_disclaim_device(void __iomem *base)
coresight_disclaim_device_unlocked(base);
CS_LOCK(base);
}
+EXPORT_SYMBOL_GPL(coresight_disclaim_device);
/* enable or disable an associated CTI device of the supplied CS device */
static int
@@ -468,6 +473,7 @@ void coresight_disable_path(struct list_head *path)
{
coresight_disable_path_from(path, NULL);
}
+EXPORT_SYMBOL_GPL(coresight_disable_path);
int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data)
{
@@ -1199,6 +1205,7 @@ int coresight_timeout(void __iomem *addr, u32 offset, int position, int value)
return -EAGAIN;
}
+EXPORT_SYMBOL_GPL(coresight_timeout);
struct bus_type coresight_bustype = {
.name = "coresight",
@@ -1355,6 +1362,7 @@ bool coresight_loses_context_with_cpu(struct device *dev)
return fwnode_property_present(dev_fwnode(dev),
"arm,coresight-loses-context-with-cpu");
}
+EXPORT_SYMBOL_GPL(coresight_loses_context_with_cpu);
/*
* coresight_alloc_device_name - Get an index for a given device in the
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-01 7:17 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 7:14 [PATCH v1 00/21] coresight: allow to build coresight as modules Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 01/21] coresight: cpu_debug: add module name in Kconfig Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 02/21] coresight: cpu_debug: define MODULE_DEVICE_TABLE Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 03/21] coresight: use IS_ENABLED for CONFIGs that may be modules Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 04/21] coresight: add coresight prefix to barrier_pkt Tingwei Zhang
2020-07-01 7:14 ` Tingwei Zhang [this message]
2020-07-01 7:14 ` [PATCH v1 06/21] Allow to build coresight-stm as a module, for ease of development Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 07/21] coresight: allow etm3x to be built as a module Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 08/21] coresight: allow etm4x " Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 09/21] coresight: allow etb " Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 10/21] coresight: allow tpiu " Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 11/21] coresight: allow tmc " Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 12/21] coresight: remove multiple init calls from funnel driver Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 13/21] coresight: remove multiple init calls from replicator driver Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 14/21] coresight: allow funnel and replicator drivers to be built as modules Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 15/21] coresight: cti: add function to register cti associate ops Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 16/21] coresight: allow cti to be built as a module Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 17/21] coresight: tmc-etr: add function to register catu ops Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 18/21] coresight: allow catu drivers to be built as modules Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 19/21] coresight: disable trace path with device being removed Tingwei Zhang
2020-07-13 22:11 ` Mathieu Poirier
2020-07-14 1:10 ` tingwei
2020-07-01 7:14 ` [PATCH v1 20/21] coresight: allow the coresight core driver to be built as a module Tingwei Zhang
2020-07-01 7:14 ` [PATCH v1 21/21] coresight: perf: clean up perf event on device unregister path Tingwei Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200701071427.10477-6-tingwei@codeaurora.org \
--to=tingwei@codeaurora.org \
--cc=alexander.shishkin@linux.intel.com \
--cc=coresight@lists.linaro.org \
--cc=gregkh@linuxfoundation.org \
--cc=jinlmao@codeaurora.org \
--cc=kim.phillips@arm.com \
--cc=leo.yan@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux@armlinux.org.uk \
--cc=mathieu.poirier@linaro.org \
--cc=rdunlap@infradead.org \
--cc=saiprakash.ranjan@codeaurora.org \
--cc=suzuki.poulose@arm.com \
--cc=tsoni@codeaurora.org \
--cc=ykaukab@suse.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).