From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F074C433DF for ; Wed, 1 Jul 2020 16:29:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DFB7820781 for ; Wed, 1 Jul 2020 16:29:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="iPrEAqd1"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZyLvsQxi" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DFB7820781 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GX7ncUykgCrvo2lCJFCCn6SSA0/fwiQK3uO0D+C0nuw=; b=iPrEAqd1nsjzTZftstAbQGkIt DNSPMTIQDseL1MA5cHvh128GFNhseg/A+ImQTM1v12oKBSLtTQZTdgdULkpV1J019OMSglP6o09bB UEAuo0DLZiscV3sl4a/YYL0s9xlv3j1GXESK5l40V3std3/ofrSTg8088V05aCGD3KEEt9mvFwShV 3HvynjQObH/c6i4xWAoKF33S484q9wK0elcXMxtD9RPrSxilsSUS84j65jikiJv5HsjNdlUZ1mQqN k8cQr06oZrMxFfGhnkeR01W76kKCqQ/lyCY3HeCI6oPi+EkfMOSZrYda/6Se7ze8i8wmNwAWoickP X13tSvzPQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqfaE-0006ZI-T2; Wed, 01 Jul 2020 16:27:38 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqfaD-0006YV-2v for linux-arm-kernel@lists.infradead.org; Wed, 01 Jul 2020 16:27:37 +0000 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A74B620781; Wed, 1 Jul 2020 16:27:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1593620856; bh=NfjeuiXZ8tAmudcEMQ6pL0+xAmALNx5dxsGvAnYC+fg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ZyLvsQxiv4lY7HTRALNQQmLX2f1Wfopm6NOfAT0hXs+VgVzz3dOyELpGpI2sJOaBY k6I7Ydh79upMz+Cdw0An2kNWU+EdEcU7fLT6BXdOrlXUcE2vEV/CqiniCQNNjlnUds VpqaZn6xXLeFicY0meXDZ1VpCy3NVSv8uPRcTIk0= Date: Wed, 1 Jul 2020 17:27:32 +0100 From: Will Deacon To: Marc Zyngier Subject: Re: Query regarding ERRATUM_1418040 Message-ID: <20200701162731.GA15317@willie-the-truck> References: <1ce7dad5-a981-5968-cc34-7648faea8636@codeaurora.org> <062be27686369d28bd2054a54c307400@misterjones.org> <20200617112542.GB3503@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200701_122737_305490_B46EF9D5 X-CRM114-Status: GOOD ( 25.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neeraj Upadhyay , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 17, 2020 at 03:29:46PM +0100, Marc Zyngier wrote: > On 2020-06-17 12:25, Will Deacon wrote: > > On Wed, Jun 17, 2020 at 12:19:16PM +0100, Marc Zyngier wrote: > > > On 2020-06-17 09:55, Neeraj Upadhyay wrote: > > > > I have query regarding the errata 1418040 [1]. Here, on kernel exit to > > > > EL0 64 bit mode, will it always enable ARCH_TIMER_USR_VCT_ACCESS_EN; > > > > and override any other erratas, which might require EL0 direct vct > > > > access to be disabled for 64 bit also? > > > > > > So far, I am not aware of any erratum that would require traps of > > > CNTVCT_EL0 > > > to EL1 when running AArch64 userspace for CPUs that are affected by > > > ARM-1418040. If such an erratum exists, it would have to be handled > > > separately. > > > > > > > Also, this errata applies > > > > mitigation for all CPUs (on return to 32 bit EL0), even if, not all > > > > cpus are impacted by the errata? > > > > > > Indeed. There isn't much we can do to avoid it here, unless you want > > > to read > > > some per-CPU variable that tells you whether the CPU is affected. > > > This would > > > add to the cost of the mitigation , and isn't an appealing prospect. > > > > Hmm, but in conjunction with the previous point, doesn't this mean if > > some CPUs are affected by an erratum which requires CNTVCT trapping for > > AArch64 and others are affected by 1418040, then the former won't > > actually > > be trapped? > > Indeed. Having CPUs that require opposite workarounds is one of the many > fascinating aspects of BL systems... :-/ Does such a system exist today? I don't know, but it feels like we should either address the issue of scream loudly if we detect it! > > Maybe we should preserve ARCH_TIMER_USR_VCT_ACCESS_EN for AArch64 tasks > > instead of setting it unconditionally? > > We'd still need something when switching from an AArch32 task to an AArch64 > one. I guess we'd either need to re-enable it on entry from a 32bit task, or > implement some sort of per-CPU, per-ISA state to be restored on return to > userspace. I think re-enabling on entry from a 32-bit task would be the easiest thing to do. Since you're playing with 32-bit timer bugs atm, do you fancy taking a look ;) Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel