From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1F16C433E0 for ; Mon, 6 Jul 2020 12:11:18 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6D0202070C for ; Mon, 6 Jul 2020 12:11:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="MgyVENF9"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="dWgTFa6h" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6D0202070C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=okw81CrW6O4cbHqS+ZQBRfVlpogxwg29vYM77wri3h0=; b=MgyVENF9BoPAUQOeV1YBzrhTX D93zZGEbZW9wQMfj1uRcxcP+Hh9DdyBfkaCQR2tqOxSc9Tf0C0RrdQx/iPxnsZ9Ge7w1074Lhp2R/ k1zpaMeBCmxxA95VEizZEDVXP10fBPgfIeZiB6Vfa5o8kLpVtdaEFeiZ6GqVcqZ7sDTXoOAvBwVNS 2iSIEj39SO7hZtIACjau1kM+fLtDv5q6hJ+mUAb9kcvDW0vwsHd6ClqQgbgzp/aBzCJ6BubYqyWpu XukJW6U2eIR5Pa5E5Jkm0Mv3Vpg2gn05rJ6VjM3H4qnpZmtDTDaOb/Xag4wDB6aHz5t1u8nAAn3ic iYjcocjMg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jsPwY-0005J6-0l; Mon, 06 Jul 2020 12:09:54 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jsPwW-0005IO-11 for linux-arm-kernel@lists.infradead.org; Mon, 06 Jul 2020 12:09:52 +0000 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 35F3D2070C; Mon, 6 Jul 2020 12:09:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1594037390; bh=fNjKa4kbsc+iVj1riW+WC6/GVzvHjq3oKYxF1/ZznpQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=dWgTFa6h74GTzA9YbZliHBkfGzzP8MtEGCvdzpUfq9prPFxJcUpJeWeC3hiEvlgTm EDwaLaYPkls+ZD50dp2VLd8z6gxhxuBr2NoTlJMoyKgY0PY+5rQpPhCOzzGuA9wqS0 Qi7HmQ6y+Kq2lVnSC2jJGGuBQCLO1VRie7vtbbrA= Date: Mon, 6 Jul 2020 13:09:47 +0100 From: Will Deacon To: Marc Zyngier Subject: Re: Query regarding ERRATUM_1418040 Message-ID: <20200706120946.GA23341@willie-the-truck> References: <1ce7dad5-a981-5968-cc34-7648faea8636@codeaurora.org> <062be27686369d28bd2054a54c307400@misterjones.org> <20200617112542.GB3503@willie-the-truck> <20200701162731.GA15317@willie-the-truck> <4196efaea5fbdf11dd6fa3ba460967d3@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4196efaea5fbdf11dd6fa3ba460967d3@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200706_080952_237624_9A654B12 X-CRM114-Status: GOOD ( 33.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neeraj Upadhyay , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 02, 2020 at 09:19:04AM +0100, Marc Zyngier wrote: > On 2020-07-01 17:27, Will Deacon wrote: > > On Wed, Jun 17, 2020 at 03:29:46PM +0100, Marc Zyngier wrote: > > > On 2020-06-17 12:25, Will Deacon wrote: > > > > Hmm, but in conjunction with the previous point, doesn't this mean if > > > > some CPUs are affected by an erratum which requires CNTVCT trapping for > > > > AArch64 and others are affected by 1418040, then the former won't > > > > actually > > > > be trapped? > > > > > > Indeed. Having CPUs that require opposite workarounds is one of the > > > many > > > fascinating aspects of BL systems... :-/ Does such a system exist > > > today? > > > > I don't know, but it feels like we should either address the issue of > > scream > > loudly if we detect it! > > I have no idea how you plan to detect that. You'd end up having to have workarounds know about each other and, yes, it would be awful. > > I think re-enabling on entry from a 32-bit task would be the easiest > > thing to > > do. Since you're playing with 32-bit timer bugs atm, do you fancy taking > > a > > look ;) > > I came up with this, tested in a guest only by fudging the detection > code (I don't have the offending HW at hand). The use of branches vs > NOPs is debatable, no strong opinion here. > > M. > > From 81126933d6c990dac7213d0ec66c4a9df21fe8b8 Mon Sep 17 00:00:00 2001 > From: Marc Zyngier > Date: Wed, 1 Jul 2020 21:29:24 +0100 > Subject: [PATCH] arm64: Rework ARM_ERRATUM_1414080 handling > > The current handling of erratum 1414080 has the side effect that > cntkctl_el1 can get changed for both 32 and 64bit tasks. > > This isn't a problem so far, but if we ever need to mitigate another > of these errata on the 64bit side, we'd better keep the messing with > cntkctl_el1 local to 32bit tasks. > > For that, make sure that on entering the kernel from a 32bit tasks, > userspace access to cntvct gets enabled, and disabled returning to > userspace, while it never gets changed for 64bit tasks. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kernel/entry.S | 44 +++++++++++++++++++++++++-------------- > 1 file changed, 28 insertions(+), 16 deletions(-) Mostly looks fine, just some small nits below. Looking at it now, though, I suspect it would make more sense to do this at context-switch. We can do that later on. > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > index 5304d193c79d..357bce62c31e 100644 > --- a/arch/arm64/kernel/entry.S > +++ b/arch/arm64/kernel/entry.S > @@ -167,6 +167,19 @@ alternative_cb_end > stp x28, x29, [sp, #16 * 14] > > .if \el == 0 > + .if \regsize == 32 > + // If we come back from a 32bit task on a system affected by > + // 1418040, let's reenable userspace access to the virtual counter. > +#ifdef CONFIG_ARM64_ERRATUM_1418040 > +alternative_if_not ARM64_WORKAROUND_1418040 > + b .L__entry_wa_1418040\@ > +alternative_else_nop_endif > + mrs x0, cntkctl_el1 > + orr x0, x0, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN > + msr cntkctl_el1, x0 > +.L__entry_wa_1418040\@: nit: naming this .L__entry_skip_wa_1418040\@ would be clearer to me, as we take the branch to jump over the workaround. > +#endif > + .endif > clear_gp_regs > mrs x21, sp_el0 > ldr_this_cpu tsk, __entry_task, x20 > @@ -318,7 +331,21 @@ alternative_else_nop_endif > ldr x23, [sp, #S_SP] // load return stack pointer > msr sp_el0, x23 > tst x22, #PSR_MODE32_BIT // native task? > - b.eq 3f > + b.eq 4f > + > +#ifdef CONFIG_ARM64_ERRATUM_1418040 > +alternative_if_not ARM64_WORKAROUND_1418040 > + b 3f > +alternative_else_nop_endif > + /* > + * if (x22.mode32 == 1) > + * cntkctl_el1.el0vcten = 0 > + */ I think we can probably drop this comment now, as I find it more confusing that helpful. > + mrs x1, cntkctl_el1 > + bfi x1, xzr, #1, #1 // ARCH_TIMER_USR_VCT_ACCESS_EN Can you use BIC here? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel