From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C598C433E0 for ; Wed, 8 Jul 2020 12:19:16 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 10FCE206C3 for ; Wed, 8 Jul 2020 12:19:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="yOFasE9i" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 10FCE206C3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VcsoYup53t1GfR34KkKtvSEwTfyauXAehRuTxm69Ejo=; b=yOFasE9iqTiY4SxMSdDRMF488 GZjoGzzIqPWC1EKhznefpXaMybErZ/GC9ILHPgJdKc2IyfcyFIZ0B32BrTzkDwQFZ/Gp4Uf+byH89 KELP9NyoAxe3FSm2oZ1J9ZCO4aWI/BPoxtbCCKvEPH+wBh/5WJ5Pih3pMagZGgAdEEJN7u5vSfIj7 /79D4ejDShgcW3qy9yZNVKwUOYyXtfgraH3kQc0rGW8NYQualrFR+8UNYYyqObJaCvRKp+xjsJJjn Tp+nfIyOqonUXyuoMwiG7d97sbkH/iNeWHfrawtX3f5S2kUTXqeiFcHdBHOc1wI+NJH7dAgG7EX21 HCPSv3IOg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jt91C-0004xV-DI; Wed, 08 Jul 2020 12:17:42 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jt918-0004wd-GO for linux-arm-kernel@lists.infradead.org; Wed, 08 Jul 2020 12:17:40 +0000 Received: from gaia (unknown [95.146.230.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 81D74206C3; Wed, 8 Jul 2020 12:17:35 +0000 (UTC) Date: Wed, 8 Jul 2020 13:17:33 +0100 From: Catalin Marinas To: David Hildenbrand Subject: Re: [PATCH v6 07/26] mm: Preserve the PG_arch_* flags in __split_huge_page_tail() Message-ID: <20200708121732.GC6308@gaia> References: <20200703153718.16973-1-catalin.marinas@arm.com> <20200703153718.16973-8-catalin.marinas@arm.com> <16aeea8c-b5c4-0d19-2fde-f95ef8dfddc6@redhat.com> <20200706163012.GH28170@gaia> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200708_081738_639091_3BE7AE25 X-CRM114-Status: GOOD ( 26.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Christian Borntraeger , Szabolcs Nagy , Andrey Konovalov , Kevin Brodsky , Peter Collingbourne , linux-mm@kvack.org, Andrew Morton , Vincenzo Frascino , Will Deacon , Dave P Martin , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jul 06, 2020 at 07:56:43PM +0200, David Hildenbrand wrote: > On 06.07.20 18:30, Catalin Marinas wrote: > > On Mon, Jul 06, 2020 at 04:16:13PM +0200, David Hildenbrand wrote: > >> On 03.07.20 17:36, Catalin Marinas wrote: > >>> When a huge page is split into normal pages, part of the head page flags > >>> are transferred to the tail pages. However, the PG_arch_* flags are not > >>> part of the preserved set. > >>> > >>> PG_arch_1 is currently used by the arch code to handle cache maintenance > >>> for user space (either for I-D cache coherency or for D-cache aliases > >>> consistent with the kernel mapping). Since splitting a huge page does > >>> not change the physical or virtual address of a mapping, additional > >>> cache maintenance for the tail pages is unnecessary. Preserving the > >>> PG_arch_1 flag from the head page in the tail pages would not break the > >>> current use-cases. > >> > >> ^ is fairly arm64 specific, no? (I remember that the semantics are > >> different e.g., on s390x). > > > > Not entirely arm64 specific. Apart from s390 and x86, I think all the > > other architectures use this flag for cache maintenance (I guess they > > followed the cachetlb.rst suggestion). My understanding of the s390 and > > x86 is that transferring this flag from the head of a compound page to > > the tail pages should not cause any issue. We don't even document > > anywhere that this flag is meant to disappear on huge page splitting. I > > guess no-one noticed because clearing it is relatively benign. > > On s390x, PG_arch_1 indicates (s390/kernel/uv.c:arch_make_page_accessible()) > - kernel page tables > - for hugetlbfs pages, that storage keys are initialized for that page > (IIRC KVM only) > - a user space page might be encrypted/secure (KVM only) > > The latter does not support hugetlbfs/THP. KVM does not support THP. So > on s390x the bit should never be set in that context and, therefore, > also won't be affected by this change. Thanks for checking. > > But if there are concerns, I'm happy to guard it with something like > > __ARCH_WANT_PG_ARCH_HEAD_TAIL (I need to think of a more suggestive > > name). > > I guess we can avoid that if we properly check+document all users. > (ignoring x86 and s390x behavior here might be dangerous, although my > gut feeling is that it's ok for both) I'll post an independent patch for PG_arch_1 to get consensus among architectures. The PG_arch_2 introduced by the MTE patches can have the new behaviour since it would only be used by arm64 initially. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel