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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 16, 2020 at 01:00:43PM +0100, Will Deacon wrote: > On Wed, 15 Jul 2020 09:06:45 +0200, Tomasz Nowicki wrote: > > The series is meant to support SMMU for AP806 and a workaround > > for accessing ARM SMMU 64bit registers is the gist of it. > > > > For the record, AP-806 can't access SMMU registers with 64bit width. > > This patches split the readq/writeq into two 32bit accesses instead > > and update DT bindings. > > > > [...] > > Applied to will (for-joerg/arm-smmu/updates), thanks! > > [1/3] iommu/arm-smmu: Call configuration impl hook before consuming features > https://git.kernel.org/will/c/6a79a5a3842b > [2/3] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 > https://git.kernel.org/will/c/f2d9848aeb9f > [3/3] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500 > https://git.kernel.org/will/c/e85e84d19b9d (note that I left patch 4 for arm-soc, as that's just updating .dts files) Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel