From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Claudiu Beznea <claudiu.beznea@microchip.com>
Cc: bbrezillon@kernel.org, sboyd@kernel.org, mturquette@baylibre.com,
linux-kernel@vger.kernel.org, ludovic.desroches@microchip.com,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 02/19] clk: at91: clk-generated: check best_rate against ranges
Date: Fri, 17 Jul 2020 11:10:36 +0200 [thread overview]
Message-ID: <20200717091036.GJ3428@piout.net> (raw)
In-Reply-To: <1594812267-6697-3-git-send-email-claudiu.beznea@microchip.com>
On 15/07/2020 14:24:10+0300, Claudiu Beznea wrote:
> Check best_rate against available clock ranges.
>
> Fixes: df70aeef6083 ("clk: at91: add generated clock driver")
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> drivers/clk/at91/clk-generated.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
> index 995a13133cfb..f8e557e0e1b8 100644
> --- a/drivers/clk/at91/clk-generated.c
> +++ b/drivers/clk/at91/clk-generated.c
> @@ -185,8 +185,8 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> __clk_get_name((req->best_parent_hw)->clk),
> req->best_parent_rate);
>
> - if (best_rate < 0)
> - return best_rate;
> + if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
> + return -EINVAL;
>
> req->rate = best_rate;
> return 0;
> --
> 2.7.4
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-07-17 9:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-15 11:24 [PATCH 00/19] clk: at91: add sama7g5 clock support Claudiu Beznea
2020-07-15 11:24 ` [PATCH 01/19] clk: at91: clk-generated: continue if __clk_determine_rate() returns error Claudiu Beznea
2020-07-17 9:09 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 02/19] clk: at91: clk-generated: check best_rate against ranges Claudiu Beznea
2020-07-17 9:10 ` Alexandre Belloni [this message]
2020-07-15 11:24 ` [PATCH 03/19] clk: at91: clk-sam9x60-pll: fix mul mask Claudiu Beznea
2020-07-17 9:11 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 04/19] clk: at91: sam9x60-pll: use frac when computing pll frequency Claudiu Beznea
2020-07-15 11:24 ` [PATCH 05/19] clk: at91: sam9x60-pll: use logical or for range check Claudiu Beznea
2020-07-17 9:13 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 06/19] clk: at91: sam9x60-pll: check fcore against ranges Claudiu Beznea
2020-07-17 9:23 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 07/19] clk: at91: sam9x60-pll: use frac when setting frequency Claudiu Beznea
2020-07-17 9:12 ` Alexandre Belloni
2020-07-20 10:34 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 08/19] clk: at91: sam9x60: fix main rc oscillator frequency Claudiu Beznea
2020-07-17 9:17 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 09/19] clk: at91: sckc: register slow_rc with accuracy option Claudiu Beznea
2020-07-15 15:39 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 10/19] clk: at91: replace conditional operator with double logical not Claudiu Beznea
2020-07-17 15:07 ` Alexandre Belloni
2020-07-20 10:36 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 11/19] clk: at91: clk-generated: pass the id of changeable parent at registration Claudiu Beznea
2020-07-16 16:57 ` Codrin.Ciubotariu
2020-07-15 11:24 ` [PATCH 12/19] clk: at91: clk-generated: add mux_table option Claudiu Beznea
2020-07-15 11:24 ` [PATCH 13/19] clk: at91: clk-master: add master clock support for SAMA7G5 Claudiu Beznea
2020-07-15 11:24 ` [PATCH 14/19] clk: at91: clk-peripheral: add support for changeable parent rate Claudiu Beznea
2020-07-15 11:24 ` [PATCH 15/19] clk: at91: clk-programmable: add mux_table option Claudiu Beznea
2020-07-15 11:24 ` [PATCH 16/19] clk: at91: add macro for pll ids mask Claudiu Beznea
2020-07-15 11:24 ` [PATCH 17/19] clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs Claudiu Beznea
2020-07-15 11:24 ` [PATCH 18/19] clk: at91: clk-utmi: add utmi support for sama7g5 Claudiu Beznea
2020-07-15 11:24 ` [PATCH 19/19] clk: at91: sama7g5: add clock " Claudiu Beznea
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200717091036.GJ3428@piout.net \
--to=alexandre.belloni@bootlin.com \
--cc=bbrezillon@kernel.org \
--cc=claudiu.beznea@microchip.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=ludovic.desroches@microchip.com \
--cc=mturquette@baylibre.com \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).