From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47D24C433DF for ; Mon, 20 Jul 2020 10:51:58 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 160582068F for ; Mon, 20 Jul 2020 10:51:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="lqqb5AIN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 160582068F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3jkQQsgZIYrx8WvwBux8NYbq62tVbD1jRpeBPT9MPnc=; b=lqqb5AINE3T1BbNabkNopiN9i aFJiavtM3ii14fRbaGOGIaUW8/sEbYRf2jmsQV1ehikOoH6Z3LIJmy+mK/qHWAoIQ9O7ehip7oYO3 +ft/wpmPTu8Oy4y+/77Yz0vvcdskbgWJd0nbSXH4K0N2AeOqXf0FJgBTTIxgybVZYinLqZhPiWZjN Dzk4BvkJNYh5t0WBp+JsHUzSlFeku7frFBKYJZFeafq5wmNyymW4i5wI9pAuDYRAW3cgaOuEbRfrX zCj04M3bvB3RYqoo12ws7DQF53ZqupCIp7pbU+PJHvf0nUOkIPHwwnlrby/ba9WG979zeHfK4+vBP EqsKOzhVQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxTNQ-0003hP-RO; Mon, 20 Jul 2020 10:50:32 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxTNN-0003gr-Qv for linux-arm-kernel@lists.infradead.org; Mon, 20 Jul 2020 10:50:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 274D8D6E; Mon, 20 Jul 2020 03:50:27 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.4.206]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 361383F66E; Mon, 20 Jul 2020 03:50:26 -0700 (PDT) Date: Mon, 20 Jul 2020 11:50:19 +0100 From: Mark Rutland To: Will Deacon Subject: Re: [PATCH v3 1/3] arm64: perf: Add support caps in sysfs Message-ID: <20200720105019.GA54220@C02TD0UTHF1T.local> References: <1592487344-30555-1-git-send-email-zhangshaokun@hisilicon.com> <20200720101518.GA11516@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200720101518.GA11516@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200720_065029_919866_8676114E X-CRM114-Status: GOOD ( 17.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shaokun Zhang , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jul 20, 2020 at 11:15:19AM +0100, Will Deacon wrote: > On Thu, Jun 18, 2020 at 09:35:42PM +0800, Shaokun Zhang wrote: > > +static umode_t > > +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr, > > + int unused) > > +{ > > + int pmuver = armv8pmu_get_pmu_version(); > > + > > + if (pmuver >= ID_AA64DFR0_PMUVER_8_4) > > + return attr->mode; > > Is this sufficient? I'm a bit confused by the text in the Arm ARM that says: > > | If ARMv8.4-PMU is implemented: > | * If STALL_SLOT is not implemented, it is IMPLEMENTATION DEFINED whether > | the PMMIR System registers are implemented. > | * If STALL_SLOT is implemented, then the PMMIR System registers are > | implemented. > > whereas the register description for PMMIR_EL1 says: > > | This register is present only when ARMv8.4-PMU is implemented. I think this is trying to say that when ARMv8.4-PMU is not implemented, PMMIR definitely isn't implemented (i.e. the the presence of PMMIR_EL1 implies the presence of ARMv8.4-PMU). > Mark -- please could you clarify whether or not we need to check STALL_SLOT > as well as the PMUVer? Given the explciit wording that it's IMP DEF, I suspect that we need to check both. I'll go chase this up. Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel