From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97FACC433E2 for ; Tue, 21 Jul 2020 08:22:56 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 66D4220714 for ; Tue, 21 Jul 2020 08:22:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ih/hH1ww"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="JWwkF0Yi" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 66D4220714 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ge3DhbVKNuHunGEYH/Eg30qohS2UdwStZmzUWtV2iuo=; b=ih/hH1ww2/78JX9Aezx62GsgQ 2hWBC4kTuD6kyCujTMPYHOX0AH2h9QSz/foOqniMs6has6Xl1LFdN+wO/WLVa0dp6Hq9SDfafeHSY v2NiVkBEgjkJ33B5l6Df7mMdH3rkYZpkax3kJT63db36ihS557zk3MDl3TTkr2EZFsZEqJ1by5JNb tqBMlyJvUsFyQLx5ld7YxCBtzuZjpY3FEdQyqj4TSImvZ0j6cdu3ymBqgGDEQPd2Sv5sdwuxtK6Dc PuyNbPUC3wXOiqDNmIHW0WabNuc94dzzM8em5OJM/owmuqqV0kZ4IDh/P0xMbGP034YczPVPJa+B2 kEMQJQnuw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxnWZ-0004wu-VG; Tue, 21 Jul 2020 08:21:20 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxnWX-0004wF-E9 for linux-arm-kernel@lists.infradead.org; Tue, 21 Jul 2020 08:21:18 +0000 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0037420714; Tue, 21 Jul 2020 08:21:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595319676; bh=ZtdKCto3UpbSCIq/bHL/P0V5SjsMXr5jdyurHxmTsbI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=JWwkF0YicIrmDqwAXFWRMkSrz3yn31dGF/4CFgogy90LRr8Q5aszdfZ3naa0UP2NZ ETuQkrW5NheReHtlslqz5vKPDKY2MJUAsvWQwtzqmqJnz9J0VlM4FvHuPE5++i4NXz byfk2gtCE2eQEdFyqnPhkuixj8eAEqSG7k1LTs4w= Date: Tue, 21 Jul 2020 09:21:13 +0100 From: Will Deacon To: Shaokun Zhang Subject: Re: [PATCH v4 1/2] arm64: perf: Add support caps in sysfs Message-ID: <20200721082112.GA13045@willie-the-truck> References: <1595317488-50814-1-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1595317488-50814-1-git-send-email-zhangshaokun@hisilicon.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200721_042117_676057_638467A8 X-CRM114-Status: GOOD ( 21.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 21, 2020 at 03:44:47PM +0800, Shaokun Zhang wrote: > ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events, > like STALL_SLOT etc, are related to it. Let's add a caps directory to > /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from > PMMIR_EL1 registers in this entry. The user programs can get the slots > from sysfs directly. > > Cc: Will Deacon > Cc: Mark Rutland > Signed-off-by: Shaokun Zhang > --- > ChangeLog in v4: > * Address Will's comments. > > ChangeLog in v3: > * Fix one typo in patch3 > > ChangeLog in v2: > * Add caps entry in sysfs > * Fix the PMU events typos > * Add one new patch to correct event ID in sysfs > > arch/arm64/include/asm/sysreg.h | 2 + > arch/arm64/kernel/perf_event.c | 125 ++++++++++++++++++++++++++++------------ > include/linux/perf/arm_pmu.h | 1 + > 3 files changed, 91 insertions(+), 37 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 463175f80341..56c45a9207c7 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -321,6 +321,8 @@ > #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) > #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) > > +#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) > + > #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) > #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > index 4d7879484cec..ed0012979271 100644 > --- a/arch/arm64/kernel/perf_event.c > +++ b/arch/arm64/kernel/perf_event.c > @@ -277,6 +277,51 @@ static struct attribute_group armv8_pmuv3_format_attr_group = { > .attrs = armv8_pmuv3_format_attrs, > }; > > +static int armv8pmu_get_pmu_version(void) > +{ > + int pmuver; > + u64 dfr0; > + > + dfr0 = read_sysreg(id_aa64dfr0_el1); > + pmuver = cpuid_feature_extract_unsigned_field(dfr0, > + ID_AA64DFR0_PMUVER_SHIFT); > + > + return pmuver; > +} > + > +static umode_t > +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr, > + int unused) > +{ > + int pmuver = armv8pmu_get_pmu_version(); > + > + if (pmuver >= ID_AA64DFR0_PMUVER_8_4) > + return attr->mode; > + > + return 0; > +} > + > +static ssize_t slots_show(struct device *dev, struct device_attribute *attr, > + char *buf) > +{ > + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF; I'm still worried that this might trigger an UNDEF and panic the kernel if STALL_SLOTS is not supported. The Arm ARM isn't clear about the behaviour, so I think we have to assume the worst and check that STALL_SLOTS is supported as well in armv8pmu_caps_attr_is_visible(). In other words, I think we have to check PMCEID1_EL0 as well as AA64DFR0_EL1. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel