From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE20EC433E1 for ; Tue, 21 Jul 2020 12:18:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7747B22482 for ; Tue, 21 Jul 2020 12:18:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="I6W1z7hc" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7747B22482 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DojsWVoHcBnJbatOwsfihU7pJtOJ5upvLaYL8XiGdGc=; b=I6W1z7hcDsfJR+aS9qgtcbf1W 7T2Cj7rlL4FULClPVFhuplbOmeCSBZr409rURtnqL46YE9r0RQwN9+k8dNPoWWA0RRzMFL5rQa/gj qNne5imgbbxYNS7FtMovZlfB2JTQ0mzCYbNS1gKBE312UxbGc7mlu34doR4yBQ9glIsIUV/cN1eFD PzDYBv4SjzU5K8KL0J5Maz1DMWA2HxCwRqPLTailqcjJFvFMkVNlykf8Y+uwp5bmy1y/Le5WWoJ3z 7OCT+NlbgDkoETHp10Txdx6zVJ5ErYMEQqo+T35m778twomDCls/E+ZcN22X4IUP7+mpYAICZ4AnW rub67Z9Ag==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxrD1-0002D4-IW; Tue, 21 Jul 2020 12:17:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jxrCz-0002CW-BU for linux-arm-kernel@lists.infradead.org; Tue, 21 Jul 2020 12:17:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7BA45101E; Tue, 21 Jul 2020 05:17:20 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.3.181]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7A96C3F66E; Tue, 21 Jul 2020 05:17:19 -0700 (PDT) Date: Tue, 21 Jul 2020 13:17:16 +0100 From: Mark Rutland To: Shaokun Zhang Subject: Re: [PATCH v5 1/2] arm64: perf: Add support caps in sysfs Message-ID: <20200721121716.GB84703@C02TD0UTHF1T.local> References: <20200721082112.GA13045@willie-the-truck> <1595328573-12751-1-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1595328573-12751-1-git-send-email-zhangshaokun@hisilicon.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200721_081721_449625_18691DD0 X-CRM114-Status: GOOD ( 15.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 21, 2020 at 06:49:32PM +0800, Shaokun Zhang wrote: > ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events, > like STALL_SLOT etc, are related to it. Let's add a caps directory to > /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from > PMMIR_EL1 registers in this entry. The user programs can get the slots > from sysfs directly. > > Cc: Will Deacon > Cc: Mark Rutland > Signed-off-by: Shaokun Zhang [...] > +static int armv8pmu_get_pmu_version(void) > +{ > + int pmuver; > + u64 dfr0; > + > + dfr0 = read_sysreg(id_aa64dfr0_el1); > + pmuver = cpuid_feature_extract_unsigned_field(dfr0, > + ID_AA64DFR0_PMUVER_SHIFT); > + > + return pmuver; > +} > + > +static umode_t > +armv8pmu_caps_attr_is_visible(struct kobject *kobj, struct attribute *attr, > + int unused) > +{ > + int pmuver = armv8pmu_get_pmu_version(); > + u32 pmceid1 = read_sysreg(pmceid1_el0); > + > + /* Check the PMU version is >= v8.4 and STALL_SLOT is implemented */ > + if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid1 & BIT(31))) > + return attr->mode; > + > + return 0; > +} > + > +static ssize_t slots_show(struct device *dev, struct device_attribute *attr, > + char *buf) > +{ > + int slots = read_sysreg_s(SYS_PMMIR_EL1) & 0xFF; > + > + return snprintf(buf, PAGE_SIZE, "%d\n", slots); > +} You'll need to use the snapshots of these fields we take at probe time; it's not safe to use read_sysreg() here as on a system with heterogeneous CPUs this code can be running on one CPU while it's printing information for another CPU. Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel