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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id m19sm18547881pgd.13.2020.07.21.08.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2020 08:01:15 -0700 (PDT) Date: Tue, 21 Jul 2020 09:01:13 -0600 From: Mathieu Poirier To: Sai Prakash Ranjan Subject: Re: [PATCH] arm64: dts: qcom: sdm845: Support ETMv4 power management Message-ID: <20200721150113.GB1216561@xps15> References: <20200721071343.2898-1-saiprakash.ranjan@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200721071343.2898-1-saiprakash.ranjan@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200721_110118_445489_5AD7361D X-CRM114-Status: GOOD ( 14.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Suzuki K Poulose , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Andy Gross , linux-arm-kernel@lists.infradead.org, Mike Leach Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 21, 2020 at 12:43:43PM +0530, Sai Prakash Ranjan wrote: > Add "arm,coresight-loses-context-with-cpu" property to coresight > ETM nodes to avoid failure of trace session because of losing > context on entering deep idle states. > > Signed-off-by: Sai Prakash Ranjan > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) Reviewed-by: Mathieu Poirier > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index e506793407d8..0b5f063dcaea 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -3016,6 +3016,7 @@ etm@7040000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3035,6 +3036,7 @@ etm@7140000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3054,6 +3056,7 @@ etm@7240000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3073,6 +3076,7 @@ etm@7340000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3092,6 +3096,7 @@ etm@7440000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3111,6 +3116,7 @@ etm@7540000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3130,6 +3136,7 @@ etm@7640000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3149,6 +3156,7 @@ etm@7740000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel