From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E82C7C433E4 for ; Mon, 27 Jul 2020 10:31:23 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B7D5F2075A for ; Mon, 27 Jul 2020 10:31:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="LHjPSEfd"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="2rLyj2Xx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B7D5F2075A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VZjhaH3J1y3hUVBAUX79lIWy2E1uQiPLeMMCKOU3Pb8=; b=LHjPSEfdoxUwqc0eo8ZVMW9EE CSQizkCQPAZrcpD/D8y9wDkzdmAEq96gGWB7eVPJJ/p2EM/zGEZNE2Wj45jKQrmJMWxmxHyNhWFCK ZcmQvUbrgHwOnnLihxJs9uJJ72vv0ylnThETyLvdLGQKCpU1I4npKV52EEc+VWEPIXNUzReNbyAqf Y9aTYqPMbxuPiGwdvkB5/kq6cVSb/DknHBwt4t3FLsKLRaE/OHhdxkKUiqmi824HQSeX6g2bCDHeM 0Su+2J4OalZmJAJWxjxHGE5REif6dLXVUWkxZFyO4CIXzWeR6WVsb7b266FjOD8EyTLVRQ4zIId// 5TbPY7Gzw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k00OX-0002Bg-Gy; Mon, 27 Jul 2020 10:30:09 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k00OS-0002AT-Nt for linux-arm-kernel@lists.infradead.org; Mon, 27 Jul 2020 10:30:06 +0000 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 11B5320759; Mon, 27 Jul 2020 10:30:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595845802; bh=bBIdOR8KerXNgJkBaW0BIuN1kZZAT3n4JUAKZMpujJY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=2rLyj2Xxpt2RnkadfmU2HeIRx0je9bDHuu+LW5EkDgXIQhKdeEu9OY71fhmTRZCFr Xux6tp0YFApRp6VAYTPeL7wAAy4okEbnq2yQbUvQIhkof9cTBWU2xdiMqLblHyR4Um tMtFzKQceI9qd9YnQy9B1D3TbwD6ZUShIL7jzi0U= Date: Mon, 27 Jul 2020 11:29:57 +0100 From: Will Deacon To: Marc Zyngier Subject: Re: [PATCH 6/7] KVM: arm64: Handle stage-2 faults on stage-1 page-table walks earlier Message-ID: <20200727102957.GA20194@willie-the-truck> References: <20200724143506.17772-1-will@kernel.org> <20200724143506.17772-7-will@kernel.org> <87r1sywg4h.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87r1sywg4h.wl-maz@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200727_063004_989576_F7FCEA11 X-CRM114-Status: GOOD ( 21.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki Poulose , Quentin Perret , James Morse , kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Jul 26, 2020 at 02:38:38PM +0100, Marc Zyngier wrote: > On Fri, 24 Jul 2020 15:35:05 +0100, > Will Deacon wrote: > > > > Stage-2 faults on stage-1 page-table walks can occur on both the I-side > > and the D-side. It is IMPLEMENTATATION DEFINED whether they are reported > > as reads or writes and, in the case that they are generated by an AT > > instruction, they are reported with the CM bit set. > > > > All of this deeply confuses the logic in kvm_handle_guest_abort(); > > userspace may or may not see the fault, depending on whether it occurs > > on the data or the instruction side, and an AT instruction may be skipped > > if the translation tables are held in a read-only memslot. > > Yuk, that's indeed ugly. Well spotted. I guess the saving grace is > that a S2 trap caused by an ATS1 instruction will be reported as > S1PTW+CM, while the fault caused by a CMO is reported as *either* > S1PTW *or* CM, but never both. Hmm, is that right? If the translation faults at S2 for a CM instruction, wouldn't it have both bits set? > > Move the handling of stage-2 faults on stage-1 page-table walks earlier > > so that they consistently result in either a data or an instruction abort > > being re-injected back to the guest. > > The instruction abort seems to be happening as the side effect of > executing outside of a memslot, not really because of a S1PTW. Not sure about that. If the instruction fetch generates an S2 abort during translation, then we could be executing from within a memslot; it's the location of the page-tables that matters. However, I think that means things still aren't quite right with my patches because we can end up calling io_mem_abort() from an instruction abort, which won't have enough syndrome information to do anything useful. Hmm. Stepping back, here's what I _think_ we want, although see the '(?)' bits where I'm particularly unsure: S2 instruction abort: * Not in memslot: inject external iabt to guest * In R/O memslot: - S2 fault on S1 walk: either EXIT_NISV or inject external iabt to guest (?) S2 data abort: * Not in memslot: - S2 fault on S1 walk: inject external dabt to guest - Cache maintenance: skip instr - Syndrome valid EXIT_MMIO - Syndrome invalid EXIT_NISV * In R/O memslot: - S2 fault on S1 walk: either EXIT_NISV or inject external dabt to guest (?) - Access is write (including cache maintenance (?)): - Syndrome valid EXIT_MMIO - Syndrome invalid EXIT_NISV Everything else gets handled by handle_access_fault()/user_mem_abort(). What do you think? > I wonder whether these S1PTW faults should be classified as external > aborts instead (because putting your page tables outside of a memslot > seems a bit bonkers). I think that's what this patch does, since we end up in kvm_inject_dabt(). Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel