* [PATCH 02/16] dt-bindings: microchip: atmel, at91rm9200-tcb: add sama5d2 compatible
2020-07-23 15:26 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Daniel Lezcano
@ 2020-07-23 15:26 ` Daniel Lezcano
2020-07-23 15:26 ` [PATCH 03/16] ARM: dts: at91: sama5d2: add TCB GCLK Daniel Lezcano
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Daniel Lezcano @ 2020-07-23 15:26 UTC (permalink / raw)
To: tglx
Cc: Rob Herring, Alexandre Belloni,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Ludovic Desroches, Rob Herring,
moderated list:ARM/Microchip AT91 SoC support
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
The sama5d2 TC block TIMER_CLOCK1 is different from the at91sam9x5 one.
Instead of being MCK / 2, it is the TCB GCLK.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200710230813.1005150-3-alexandre.belloni@bootlin.com
---
.../soc/microchip/atmel,at91rm9200-tcb.yaml | 42 +++++++++++++++----
1 file changed, 33 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
index 9d680e0b9109..d226fd7d5258 100644
--- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
@@ -19,6 +19,7 @@ properties:
- enum:
- atmel,at91rm9200-tcb
- atmel,at91sam9x5-tcb
+ - atmel,sama5d2-tcb
- const: simple-mfd
- const: syscon
@@ -36,15 +37,6 @@ properties:
description:
List of clock names. Always includes t0_clk and slow clk. Also includes
t1_clk and t2_clk if a clock per channel is available.
- oneOf:
- - items:
- - const: t0_clk
- - const: slow_clk
- - items:
- - const: t0_clk
- - const: t1_clk
- - const: t2_clk
- - const: slow_clk
minItems: 2
maxItems: 4
@@ -75,6 +67,38 @@ patternProperties:
- compatible
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: atmel,sama5d2-tcb
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: t0_clk
+ - const: gclk
+ - const: slow_clk
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 4
+ clock-names:
+ oneOf:
+ - items:
+ - const: t0_clk
+ - const: slow_clk
+ - items:
+ - const: t0_clk
+ - const: t1_clk
+ - const: t2_clk
+ - const: slow_clk
+
required:
- compatible
- reg
--
2.25.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 03/16] ARM: dts: at91: sama5d2: add TCB GCLK
2020-07-23 15:26 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Daniel Lezcano
2020-07-23 15:26 ` [PATCH 02/16] dt-bindings: microchip: atmel, at91rm9200-tcb: add sama5d2 compatible Daniel Lezcano
@ 2020-07-23 15:26 ` Daniel Lezcano
2020-07-23 15:26 ` [PATCH 04/16] ARM: at91: add atmel tcb capabilities Daniel Lezcano
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Daniel Lezcano @ 2020-07-23 15:26 UTC (permalink / raw)
To: tglx
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Alexandre Belloni, open list, Ludovic Desroches, Rob Herring,
moderated list:ARM/Microchip AT91 SoC support
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
The sama5d2 tcbs take an extra input clock, their gclk.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200710230813.1005150-4-alexandre.belloni@bootlin.com
---
arch/arm/boot/dts/sama5d2.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index ab550d69db91..996143e966d8 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -499,23 +499,23 @@ macb0: ethernet@f8008000 {
};
tcb0: timer@f800c000 {
- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+ compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;
- clock-names = "t0_clk", "slow_clk";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>;
+ clock-names = "t0_clk", "gclk", "slow_clk";
};
tcb1: timer@f8010000 {
- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+ compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf8010000 0x100>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;
- clock-names = "t0_clk", "slow_clk";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>;
+ clock-names = "t0_clk", "gclk", "slow_clk";
};
hsmc: hsmc@f8014000 {
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 04/16] ARM: at91: add atmel tcb capabilities
2020-07-23 15:26 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Daniel Lezcano
2020-07-23 15:26 ` [PATCH 02/16] dt-bindings: microchip: atmel, at91rm9200-tcb: add sama5d2 compatible Daniel Lezcano
2020-07-23 15:26 ` [PATCH 03/16] ARM: dts: at91: sama5d2: add TCB GCLK Daniel Lezcano
@ 2020-07-23 15:26 ` Daniel Lezcano
2020-07-23 15:26 ` [PATCH 05/16] clocksource/drivers/timer-atmel-tcb: Rework 32khz clock selection Daniel Lezcano
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Daniel Lezcano @ 2020-07-23 15:26 UTC (permalink / raw)
To: tglx
Cc: Kamel Bouhara, Alexandre Belloni, open list, Ludovic Desroches,
moderated list:ARM/Microchip AT91 SoC support
From: Kamel Bouhara <kamel.bouhara@bootlin.com>
Some atmel socs have extra tcb capabilities that allow using a generic
clock source or enabling a quadrature decoder.
Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200710230813.1005150-5-alexandre.belloni@bootlin.com
---
include/soc/at91/atmel_tcb.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/soc/at91/atmel_tcb.h b/include/soc/at91/atmel_tcb.h
index c3c7200ce151..1d7071dc0bca 100644
--- a/include/soc/at91/atmel_tcb.h
+++ b/include/soc/at91/atmel_tcb.h
@@ -36,9 +36,14 @@ struct clk;
/**
* struct atmel_tcb_config - SoC data for a Timer/Counter Block
* @counter_width: size in bits of a timer counter register
+ * @has_gclk: boolean indicating if a timer counter has a generic clock
+ * @has_qdec: boolean indicating if a timer counter has a quadrature
+ * decoder.
*/
struct atmel_tcb_config {
size_t counter_width;
+ bool has_gclk;
+ bool has_qdec;
};
/**
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 05/16] clocksource/drivers/timer-atmel-tcb: Rework 32khz clock selection
2020-07-23 15:26 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Daniel Lezcano
` (2 preceding siblings ...)
2020-07-23 15:26 ` [PATCH 04/16] ARM: at91: add atmel tcb capabilities Daniel Lezcano
@ 2020-07-23 15:26 ` Daniel Lezcano
2020-07-23 15:26 ` [PATCH 06/16] clocksource/drivers/timer-atmel-tcb: Fill tcb_config Daniel Lezcano
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Daniel Lezcano @ 2020-07-23 15:26 UTC (permalink / raw)
To: tglx
Cc: Alexandre Belloni, Ludovic Desroches,
moderated list:ARM/Microchip AT91 SoC support,
open list:CLOCKSOURCE, CLOCKEVENT DRIVERS
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
On all the supported SoCs, the slow clock is always ATMEL_TC_TIMER_CLOCK5,
avoid looking it up and pass it directly to setup_clkevents.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200710230813.1005150-6-alexandre.belloni@bootlin.com
---
drivers/clocksource/timer-atmel-tcb.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 7427b07495a8..b255a4a1a36b 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -346,7 +346,7 @@ static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_id
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}
-static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, };
+static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };
static const struct of_device_id atmel_tcb_of_match[] = {
{ .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
@@ -362,7 +362,6 @@ static int __init tcb_clksrc_init(struct device_node *node)
u64 (*tc_sched_clock)(void);
u32 rate, divided_rate = 0;
int best_divisor_idx = -1;
- int clk32k_divisor_idx = -1;
int bits;
int i;
int ret;
@@ -416,12 +415,6 @@ static int __init tcb_clksrc_init(struct device_node *node)
unsigned divisor = atmel_tcb_divisors[i];
unsigned tmp;
- /* remember 32 KiHz clock for later */
- if (!divisor) {
- clk32k_divisor_idx = i;
- continue;
- }
-
tmp = rate / divisor;
pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
if (best_divisor_idx > 0) {
@@ -467,7 +460,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
goto err_disable_t1;
/* channel 2: periodic and oneshot timer support */
- ret = setup_clkevents(&tc, clk32k_divisor_idx);
+ ret = setup_clkevents(&tc, ATMEL_TC_TIMER_CLOCK5);
if (ret)
goto err_unregister_clksrc;
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 06/16] clocksource/drivers/timer-atmel-tcb: Fill tcb_config
2020-07-23 15:26 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Daniel Lezcano
` (3 preceding siblings ...)
2020-07-23 15:26 ` [PATCH 05/16] clocksource/drivers/timer-atmel-tcb: Rework 32khz clock selection Daniel Lezcano
@ 2020-07-23 15:26 ` Daniel Lezcano
2020-07-23 15:26 ` [PATCH 07/16] clocksource/drivers/timer-atmel-tcb: Stop using the 32kHz for clockevents Daniel Lezcano
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Daniel Lezcano @ 2020-07-23 15:26 UTC (permalink / raw)
To: tglx
Cc: Alexandre Belloni, Ludovic Desroches,
moderated list:ARM/Microchip AT91 SoC support,
open list:CLOCKSOURCE, CLOCKEVENT DRIVERS
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Use the tcb_config and struct atmel_tcb_config to get the timer counter
width. This is necessary because atmel_tcb_config will be extended later
on.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200710230813.1005150-7-alexandre.belloni@bootlin.com
---
drivers/clocksource/timer-atmel-tcb.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index b255a4a1a36b..423af2f9835f 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -348,9 +348,17 @@ static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_id
static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };
+static struct atmel_tcb_config tcb_rm9200_config = {
+ .counter_width = 16,
+};
+
+static struct atmel_tcb_config tcb_sam9x5_config = {
+ .counter_width = 32,
+};
+
static const struct of_device_id atmel_tcb_of_match[] = {
- { .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
- { .compatible = "atmel,at91sam9x5-tcb", .data = (void *)32, },
+ { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
+ { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
{ /* sentinel */ }
};
@@ -398,7 +406,11 @@ static int __init tcb_clksrc_init(struct device_node *node)
}
match = of_match_node(atmel_tcb_of_match, node->parent);
- bits = (uintptr_t)match->data;
+ if (!match)
+ return -ENODEV;
+
+ tc.tcb_config = match->data;
+ bits = tc.tcb_config->counter_width;
for (i = 0; i < ARRAY_SIZE(tc.irq); i++)
writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 07/16] clocksource/drivers/timer-atmel-tcb: Stop using the 32kHz for clockevents
2020-07-23 15:26 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Daniel Lezcano
` (4 preceding siblings ...)
2020-07-23 15:26 ` [PATCH 06/16] clocksource/drivers/timer-atmel-tcb: Fill tcb_config Daniel Lezcano
@ 2020-07-23 15:26 ` Daniel Lezcano
2020-07-23 15:26 ` [PATCH 08/16] clocksource/drivers/timer-atmel-tcb: Allow selecting first divider Daniel Lezcano
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Daniel Lezcano @ 2020-07-23 15:26 UTC (permalink / raw)
To: tglx
Cc: Alexandre Belloni, Ludovic Desroches,
moderated list:ARM/Microchip AT91 SoC support,
open list:CLOCKSOURCE, CLOCKEVENT DRIVERS
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Stop using the slow clock as the clock source for 32 bit counters because
even at 10MHz, they are able to handle delays up to two minutes. This
provides a way better resolution.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200710230813.1005150-8-alexandre.belloni@bootlin.com
---
drivers/clocksource/timer-atmel-tcb.c | 63 ++++++++++++++-------------
1 file changed, 33 insertions(+), 30 deletions(-)
diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 423af2f9835f..7a6474acc774 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -27,9 +27,10 @@
* - Some chips support 32 bit counter. A single channel is used for
* this 32 bit free-running counter. the second channel is not used.
*
- * - The third channel may be used to provide a 16-bit clockevent
- * source, used in either periodic or oneshot mode. This runs
- * at 32 KiHZ, and can handle delays of up to two seconds.
+ * - The third channel may be used to provide a clockevent source, used in
+ * either periodic or oneshot mode. For 16-bit counter its runs at 32 KiHZ,
+ * and can handle delays of up to two seconds. For 32-bit counters, it runs at
+ * the same rate as the clocksource
*
* REVISIT behavior during system suspend states... we should disable
* all clocks and save the power. Easily done for clockevent devices,
@@ -47,6 +48,8 @@ static struct
} tcb_cache[3];
static u32 bmr_cache;
+static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };
+
static u64 tc_get_cycles(struct clocksource *cs)
{
unsigned long flags;
@@ -143,6 +146,7 @@ static unsigned long notrace tc_delay_timer_read32(void)
struct tc_clkevt_device {
struct clock_event_device clkevt;
struct clk *clk;
+ u32 rate;
void __iomem *regs;
};
@@ -151,13 +155,6 @@ static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
return container_of(clkevt, struct tc_clkevt_device, clkevt);
}
-/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
- * because using one of the divided clocks would usually mean the
- * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
- *
- * A divided clock could be good for high resolution timers, since
- * 30.5 usec resolution can seem "low".
- */
static u32 timer_clock;
static int tc_shutdown(struct clock_event_device *d)
@@ -183,7 +180,7 @@ static int tc_set_oneshot(struct clock_event_device *d)
clk_enable(tcd->clk);
- /* slow clock, count up to RC, then irq and stop */
+ /* count up to RC, then irq and stop */
writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
@@ -205,10 +202,10 @@ static int tc_set_periodic(struct clock_event_device *d)
*/
clk_enable(tcd->clk);
- /* slow clock, count up to RC, then irq and restart */
+ /* count up to RC, then irq and restart */
writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
regs + ATMEL_TC_REG(2, CMR));
- writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
+ writel((tcd->rate + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
/* Enable clock and interrupts on RC compare */
writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
@@ -256,47 +253,55 @@ static irqreturn_t ch2_irq(int irq, void *handle)
return IRQ_NONE;
}
-static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
+static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx)
{
int ret;
struct clk *t2_clk = tc->clk[2];
int irq = tc->irq[2];
-
- ret = clk_prepare_enable(tc->slow_clk);
- if (ret)
- return ret;
+ int bits = tc->tcb_config->counter_width;
/* try to enable t2 clk to avoid future errors in mode change */
ret = clk_prepare_enable(t2_clk);
- if (ret) {
- clk_disable_unprepare(tc->slow_clk);
+ if (ret)
return ret;
- }
-
- clk_disable(t2_clk);
clkevt.regs = tc->regs;
clkevt.clk = t2_clk;
- timer_clock = clk32k_divisor_idx;
+ if (bits == 32) {
+ timer_clock = divisor_idx;
+ clkevt.rate = clk_get_rate(t2_clk) / atmel_tcb_divisors[divisor_idx];
+ } else {
+ ret = clk_prepare_enable(tc->slow_clk);
+ if (ret) {
+ clk_disable_unprepare(t2_clk);
+ return ret;
+ }
+
+ clkevt.rate = clk_get_rate(tc->slow_clk);
+ timer_clock = ATMEL_TC_TIMER_CLOCK5;
+ }
+
+ clk_disable(t2_clk);
clkevt.clkevt.cpumask = cpumask_of(0);
ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
if (ret) {
clk_unprepare(t2_clk);
- clk_disable_unprepare(tc->slow_clk);
+ if (bits != 32)
+ clk_disable_unprepare(tc->slow_clk);
return ret;
}
- clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
+ clockevents_config_and_register(&clkevt.clkevt, clkevt.rate, 1, BIT(bits) - 1);
return ret;
}
#else /* !CONFIG_GENERIC_CLOCKEVENTS */
-static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
+static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx)
{
/* NOTHING */
return 0;
@@ -346,8 +351,6 @@ static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_id
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}
-static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };
-
static struct atmel_tcb_config tcb_rm9200_config = {
.counter_width = 16,
};
@@ -472,7 +475,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
goto err_disable_t1;
/* channel 2: periodic and oneshot timer support */
- ret = setup_clkevents(&tc, ATMEL_TC_TIMER_CLOCK5);
+ ret = setup_clkevents(&tc, best_divisor_idx);
if (ret)
goto err_unregister_clksrc;
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 08/16] clocksource/drivers/timer-atmel-tcb: Allow selecting first divider
2020-07-23 15:26 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Daniel Lezcano
` (5 preceding siblings ...)
2020-07-23 15:26 ` [PATCH 07/16] clocksource/drivers/timer-atmel-tcb: Stop using the 32kHz for clockevents Daniel Lezcano
@ 2020-07-23 15:26 ` Daniel Lezcano
2020-07-23 15:26 ` [PATCH 09/16] clocksource/drivers/timer-atmel-tcb: Add sama5d2 support Daniel Lezcano
2020-07-27 14:04 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Lee Jones
8 siblings, 0 replies; 10+ messages in thread
From: Daniel Lezcano @ 2020-07-23 15:26 UTC (permalink / raw)
To: tglx
Cc: Alexandre Belloni, Ludovic Desroches,
moderated list:ARM/Microchip AT91 SoC support,
open list:CLOCKSOURCE, CLOCKEVENT DRIVERS
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
The divider selection algorithm never allowed to get index 0. It was also
continuing to look for dividers, trying to find the slow clock selection.
This is not necessary anymore.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200710230813.1005150-9-alexandre.belloni@bootlin.com
---
drivers/clocksource/timer-atmel-tcb.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 7a6474acc774..7fea134650fc 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -432,10 +432,8 @@ static int __init tcb_clksrc_init(struct device_node *node)
tmp = rate / divisor;
pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
- if (best_divisor_idx > 0) {
- if (tmp < 5 * 1000 * 1000)
- continue;
- }
+ if ((best_divisor_idx >= 0) && (tmp < 5 * 1000 * 1000))
+ break;
divided_rate = tmp;
best_divisor_idx = i;
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 09/16] clocksource/drivers/timer-atmel-tcb: Add sama5d2 support
2020-07-23 15:26 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Daniel Lezcano
` (6 preceding siblings ...)
2020-07-23 15:26 ` [PATCH 08/16] clocksource/drivers/timer-atmel-tcb: Allow selecting first divider Daniel Lezcano
@ 2020-07-23 15:26 ` Daniel Lezcano
2020-07-27 14:04 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Lee Jones
8 siblings, 0 replies; 10+ messages in thread
From: Daniel Lezcano @ 2020-07-23 15:26 UTC (permalink / raw)
To: tglx
Cc: Alexandre Belloni, Ludovic Desroches,
moderated list:ARM/Microchip AT91 SoC support,
open list:CLOCKSOURCE, CLOCKEVENT DRIVERS
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
The first divisor for the sama5d2 is actually the gclk selector. Because
the currently remaining divisors are fitting the use case, currently ensure
it is skipped.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200710230813.1005150-10-alexandre.belloni@bootlin.com
---
drivers/clocksource/timer-atmel-tcb.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 7fea134650fc..787dbebbb432 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -359,9 +359,15 @@ static struct atmel_tcb_config tcb_sam9x5_config = {
.counter_width = 32,
};
+static struct atmel_tcb_config tcb_sama5d2_config = {
+ .counter_width = 32,
+ .has_gclk = 1,
+};
+
static const struct of_device_id atmel_tcb_of_match[] = {
{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
+ { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
{ /* sentinel */ }
};
@@ -426,7 +432,10 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* How fast will we be counting? Pick something over 5 MHz. */
rate = (u32) clk_get_rate(t0_clk);
- for (i = 0; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
+ i = 0;
+ if (tc.tcb_config->has_gclk)
+ i = 1;
+ for (; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
unsigned divisor = atmel_tcb_divisors[i];
unsigned tmp;
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema
2020-07-23 15:26 ` [PATCH 01/16] dt-bindings: atmel-tcb: convert bindings to json-schema Daniel Lezcano
` (7 preceding siblings ...)
2020-07-23 15:26 ` [PATCH 09/16] clocksource/drivers/timer-atmel-tcb: Add sama5d2 support Daniel Lezcano
@ 2020-07-27 14:04 ` Lee Jones
8 siblings, 0 replies; 10+ messages in thread
From: Lee Jones @ 2020-07-27 14:04 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Rob Herring, Alexandre Belloni,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Ludovic Desroches, Rob Herring, tglx,
moderated list:ARM/Microchip (AT91) SoC support
On Thu, 23 Jul 2020, Daniel Lezcano wrote:
> From: Alexandre Belloni <alexandre.belloni@bootlin.com>
>
> Convert Atmel Timer Counter Blocks bindings to DT schema format using
> json-schema.
>
> Also move it out of mfd as it is not and has never been related to mfd.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> Link: https://lore.kernel.org/r/20200710230813.1005150-2-alexandre.belloni@bootlin.com
> ---
> .../devicetree/bindings/mfd/atmel-tcb.txt | 56 --------
Acked-by: Lee Jones <lee.jones@linaro.org>
> .../soc/microchip/atmel,at91rm9200-tcb.yaml | 131 ++++++++++++++++++
> 2 files changed, 131 insertions(+), 56 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-tcb.txt
> create mode 100644 Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply [flat|nested] 10+ messages in thread