From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEE0EC433DF for ; Thu, 30 Jul 2020 11:41:37 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A3462082E for ; Thu, 30 Jul 2020 11:41:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="tnCgB4Zb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A3462082E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kd/za/PDCFqiM2QbhGMZ2rh9SUUjqOiFFnUAC4ffYKY=; b=tnCgB4ZbC08VlvVaKYGZ+czdk OeqtAaK1gfJSdd707xxzaW38Dt7i/opVl/+NvDiNrhgRpN5W9zPjTdHN7KgjDseJXW1dSJxJcaePk 46vZUe4iLRnR+j6TAxK1gV/ecvN3MbPQb1RHI/dxxnoybx8fJBZ0yu9zgAkb+1Qidt0M+hHa4763a EuNdTkwgmmMcpyrJkIOXBhiizJJMmqo8dNHjf6NoEVipmfmbIiaxIK7S8iwo8N1zETMJ0v88Qu+t4 evX95DJ1/271LCNVCMnQ610qLlfkNQHVaNlfBbL1B98chT+M5abb8Mkw4YqHpfK4TD6M3TgoIZ0Dz YQYtZCfGg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k16v0-0005cX-0F; Thu, 30 Jul 2020 11:40:14 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k16uy-0005Z0-1k for linux-arm-kernel@lists.infradead.org; Thu, 30 Jul 2020 11:40:12 +0000 Received: from gaia (unknown [95.146.230.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 818B9207F5; Thu, 30 Jul 2020 11:40:10 +0000 (UTC) Date: Thu, 30 Jul 2020 12:40:08 +0100 From: Catalin Marinas To: David Clear Subject: Re: ARM64: Question: Supporting outer-no-allocate Message-ID: <20200730114007.GI25149@gaia> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200730_074012_159926_9C1B13D4 X-CRM114-Status: GOOD ( 18.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: will@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 17, 2020 at 03:24:31PM -0700, David Clear wrote: > I'd like to ask whether we can support the configuration of the TCR and MAIR > registers so as to select outer read-no-allocate, outer write-no-allocate on > ARM memory transactions. I recognize that this might be quite a limited > use-case so let me explain why I'm asking. > > The Pensando ASIC is a PCIE host-attached multi-100Gbps I/O chip that includes > an A72 arm64 complex for internal device management. The hardware data-path > makes extensive use of RAM for in-flight metadata, and performance is > maximized by preventing the ARM from allocating cache lines in L3 that would > evict that metadata, at the acceptable cost of increasing ARM memory latency > through L3. > > I'd like to upstream as much support for the chip as possible, but I don't > want to formally post a patch if the idea is objectionable, or if there's > a more acceptable way to accomplish the same goal. > > The simplest solution might be a new Kconfig option MMU_OUTER_NO_ALLOCATE > to choose the desired TCR and MAIR values: > > arch/arm64/include/asm/sysreg.h: > #ifndef CONFIG_MMU_OUTER_NO_ALLOCATE > #define MAIR_ATTR_NORMAL_WT UL(0x8b) > #define MAIR_ATTR_NORMAL UL(0xcf) > #else > #define MAIR_ATTR_NORMAL_WT UL(0xbb) > #define MAIR_ATTR_NORMAL UL(0xff) > #endif I'm not keen on having config options for such use-cases. In theory, we could add a command-line option but given that it's only for one driver that's not even in mainline, it doesn't have a strong case ;). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel