From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71EE1C433DF for ; Thu, 30 Jul 2020 18:02:12 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 33F8820809 for ; Thu, 30 Jul 2020 18:02:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="0pq0Hs0+"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OSeU1K2d" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 33F8820809 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=YwkuWNCKCVqjd7kEpZj45I/33DtyqrRnoHF3d080sWY=; b=0pq0Hs0+5rvMoevLN9riYEm1B 4Z0gW3b2KsseguUffcMcNWI3r11CTEp/9SGOgnqY9fhRGtZzGXI45ZHrg3daj4wY75AT9qOWfwGIM Ka5QsADtVQN1Zc9Dx6d/pi1zA+uexUXJkdRBDgad8WgvBKW/xaAu7+fD6/NtBxN8DjtlQV+oR8Lvo fxbLB7jF3wahQ+W3BRmIN53B2o6z2eUr3SYgZ3yHjJbvRFtg41W3bYcDLtyZDeZOG2oB1iPPlyjQ2 ZL4RRp9JjR7S8ookOyVRqzaO/fG4tWHT0NBc1HjMR8C/vnwT+BVGuby0PpOzDCBgjaIGsU7CQp/DJ 3JbChvgxw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k1CrF-0006mX-8O; Thu, 30 Jul 2020 18:00:45 +0000 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k1CrC-0006lt-Av for linux-arm-kernel@lists.infradead.org; Thu, 30 Jul 2020 18:00:43 +0000 Received: by mail-pl1-x642.google.com with SMTP id b9so14855289plx.6 for ; Thu, 30 Jul 2020 11:00:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=YAbIFdBDABY/iXuY15hqoTWQkh5jDcA9cKphlTXpDXY=; b=OSeU1K2dfFPDKWOoMiuL8J8qgmGnmMfm6C28NeV15zxkyshGg9Pn2+mYhFVK8fwBpA F0Zho5yBnVJBSOSQJSFH7X+q3RnhJ3VWm8kN1F5TRGN0EW7AUd7gl7+3eY0YWVYopR7M DYRXQGDLmfyr+qyTU8P3BOKf9vrGwlwjqrSuvpKrDfEOtoOFgI4oqizRFEDrv33Lo0KR KdnhwqtFz4ATwU/EKNM2QRV13vvi8hIQ8b6KGR7DOn3F1OaBxPuYdwJbbsWv9BLcaZGk WgwYomkRlk/Mh70u49DNhgLSSnWKTIz08ASRfDKbVR6ggvsPQp1r3wKGeMvteYgjVEL7 mVzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=YAbIFdBDABY/iXuY15hqoTWQkh5jDcA9cKphlTXpDXY=; b=F/kRvlzbom82ZUC3o7zF+t4vIu8cnun95a9Ui6302eXi3xg6OmsdqpMcQmuVcsPlpf DiIJAKPbRmvXOFgP6t9McJYPivJsohmTowwiMknmSjIhXz09C0dw0WCLy7vHHrRGFmIg sUuyy5UeEBycRYIHeQ5DGjTrw+giupWbV73KWWL9MtnZ6pQ6HGvUtGWpt4/Tcia1mQXG T4P124EVQ4zWBZhk5HoNxIFG3PKZzu0MQ0Lvjrc3mxoCCCmNGYNO4lyIvwGkIeyl5f6S gIXWNCgqVaTwehq9hIBlAv8aGLpGIkhKj99Pb6Fi1YQkUH/OhKFmjLiSmzxGBO2KgI8F aehg== X-Gm-Message-State: AOAM530JLC26qQYdYGkw0azLe9lVCgMD18QxkXiwD7poiLEd2KprxjdZ QCn8qM9W2RXdtvc/Il43bt+k6g== X-Google-Smtp-Source: ABdhPJz6Oh6ceXjr+WqAskWacr79G2Qt+NEOQixqHlwv4Dg7MtX5BxU8v8XnKT6IexMsvSSkL+5FqA== X-Received: by 2002:a17:90a:ff92:: with SMTP id hf18mr268933pjb.107.1596132040054; Thu, 30 Jul 2020 11:00:40 -0700 (PDT) Received: from xps15 (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id r7sm5088400pfl.186.2020.07.30.11.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2020 11:00:39 -0700 (PDT) Date: Thu, 30 Jul 2020 12:00:37 -0600 From: Mathieu Poirier To: Suzuki K Poulose Subject: Re: [RFC PATCH 05/14] coresight: Convert coresight_timeout to use access abstraction Message-ID: <20200730180037.GB3155687@xps15> References: <20200722172040.1299289-1-suzuki.poulose@arm.com> <20200722172040.1299289-6-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200722172040.1299289-6-suzuki.poulose@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200730_140042_530970_BAAB8EA0 X-CRM114-Status: GOOD ( 33.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jul 22, 2020 at 06:20:31PM +0100, Suzuki K Poulose wrote: > Convert the generic routines to use the new access abstraction layer > gradually, starting with coresigth_timeout. > > Cc: Mathieu Poirier > Cc: Mike Leach > Signed-off-by: Suzuki K Poulose > --- > drivers/hwtracing/coresight/coresight-catu.c | 2 +- > drivers/hwtracing/coresight/coresight-etb10.c | 5 +++-- > drivers/hwtracing/coresight/coresight-etm4x.c | 12 +++++++----- > drivers/hwtracing/coresight/coresight-stm.c | 2 +- > drivers/hwtracing/coresight/coresight-tmc.c | 9 ++++++--- > drivers/hwtracing/coresight/coresight-tpiu.c | 4 ++-- > drivers/hwtracing/coresight/coresight.c | 15 +++++++++------ > include/linux/coresight.h | 17 +++++++++++++---- > 8 files changed, 42 insertions(+), 24 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c > index 6299ff7b8a14..30f037d4549d 100644 > --- a/drivers/hwtracing/coresight/coresight-catu.c > +++ b/drivers/hwtracing/coresight/coresight-catu.c > @@ -401,7 +401,7 @@ static const struct attribute_group *catu_groups[] = { > > static inline int catu_wait_for_ready(struct catu_drvdata *drvdata) > { > - return coresight_timeout(drvdata->base, > + return coresight_timeout(&drvdata->csdev->access, > CATU_STATUS, CATU_STATUS_READY, 1); > } > > diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c > index 0f2735e15119..507f63c51be5 100644 > --- a/drivers/hwtracing/coresight/coresight-etb10.c > +++ b/drivers/hwtracing/coresight/coresight-etb10.c > @@ -251,6 +251,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) > { > u32 ffcr; > struct device *dev = &drvdata->csdev->dev; > + struct coresight_device *csdev = drvdata->csdev; > > CS_UNLOCK(drvdata->base); > > @@ -262,7 +263,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) > ffcr |= ETB_FFCR_FON_MAN; > writel_relaxed(ffcr, drvdata->base + ETB_FFCR); > > - if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) { > + if (coresight_timeout(&csdev->access, ETB_FFCR, ETB_FFCR_BIT, 0)) { > dev_err(dev, > "timeout while waiting for completion of Manual Flush\n"); > } > @@ -270,7 +271,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) > /* disable trace capture */ > writel_relaxed(0x0, drvdata->base + ETB_CTL_REG); > > - if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) { > + if (coresight_timeout(&csdev->access, ETB_FFSR, ETB_FFSR_BIT, 1)) { > dev_err(dev, > "timeout while waiting for Formatter to Stop\n"); > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 67deb4a4e618..d78d79940fc9 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -109,6 +109,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > int i, rc; > struct etmv4_config *config = &drvdata->config; > struct device *etm_dev = &drvdata->csdev->dev; > + struct coresight_device *csdev = drvdata->csdev; > > CS_UNLOCK(drvdata->base); > > @@ -122,7 +123,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > writel_relaxed(0, drvdata->base + TRCPRGCTLR); > > /* wait for TRCSTATR.IDLE to go up */ > - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) > + if (coresight_timeout(&csdev->access, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) > dev_err(etm_dev, > "timeout while waiting for Idle Trace Status\n"); > > @@ -209,7 +210,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > writel_relaxed(1, drvdata->base + TRCPRGCTLR); > > /* wait for TRCSTATR.IDLE to go back down to '0' */ > - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) > + if (coresight_timeout(&csdev->access, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) > dev_err(etm_dev, > "timeout while waiting for Idle Trace Status\n"); > > @@ -474,6 +475,7 @@ static void etm4_disable_hw(void *info) > struct etmv4_drvdata *drvdata = info; > struct etmv4_config *config = &drvdata->config; > struct device *etm_dev = &drvdata->csdev->dev; > + struct coresight_device *csdev = drvdata->csdev; > int i; > > CS_UNLOCK(drvdata->base); > @@ -500,7 +502,7 @@ static void etm4_disable_hw(void *info) > writel_relaxed(control, drvdata->base + TRCPRGCTLR); > > /* wait for TRCSTATR.PMSTABLE to go to '1' */ > - if (coresight_timeout(drvdata->base, TRCSTATR, > + if (coresight_timeout(&csdev->access, TRCSTATR, > TRCSTATR_PMSTABLE_BIT, 1)) > dev_err(etm_dev, > "timeout while waiting for PM stable Trace Status\n"); > @@ -1163,7 +1165,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) > etm4_os_lock(drvdata); > > /* wait for TRCSTATR.PMSTABLE to go up */ > - if (coresight_timeout(drvdata->base, TRCSTATR, > + if (coresight_timeout(&csdev->access, TRCSTATR, > TRCSTATR_PMSTABLE_BIT, 1)) { > dev_err(etm_dev, > "timeout while waiting for PM Stable Status\n"); > @@ -1247,7 +1249,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcpdcr = readl(drvdata->base + TRCPDCR); > > /* wait for TRCSTATR.IDLE to go up */ > - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { > + if (coresight_timeout(&csdev->access, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { > dev_err(etm_dev, > "timeout while waiting for Idle Trace Status\n"); > etm4_os_unlock(drvdata); > diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > index c8509cc78512..b704000c96b8 100644 > --- a/drivers/hwtracing/coresight/coresight-stm.c > +++ b/drivers/hwtracing/coresight/coresight-stm.c > @@ -270,7 +270,7 @@ static void stm_disable(struct coresight_device *csdev, > spin_unlock(&drvdata->spinlock); > > /* Wait until the engine has completely stopped */ > - coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0); > + coresight_timeout(&csdev->access, STMTCSR, STMTCSR_BUSY_BIT, 0); > > pm_runtime_put(csdev->dev.parent); > > diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c > index b49795ad6861..6036eb73dce8 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.c > +++ b/drivers/hwtracing/coresight/coresight-tmc.c > @@ -33,16 +33,19 @@ DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); > > void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > { > + struct coresight_device *csdev = drvdata->csdev; > + > /* Ensure formatter, unformatter and hardware fifo are empty */ > - if (coresight_timeout(drvdata->base, > + if (coresight_timeout(&csdev->access, > TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { > - dev_err(&drvdata->csdev->dev, > + dev_err(&csdev->dev, > "timeout while waiting for TMC to be Ready\n"); > } > } > > void tmc_flush_and_stop(struct tmc_drvdata *drvdata) > { > + struct coresight_device *csdev = drvdata->csdev; > u32 ffcr; > > ffcr = readl_relaxed(drvdata->base + TMC_FFCR); > @@ -51,7 +54,7 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata) > ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); > writel_relaxed(ffcr, drvdata->base + TMC_FFCR); > /* Ensure flush completes */ > - if (coresight_timeout(drvdata->base, > + if (coresight_timeout(&csdev->access, > TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { > dev_err(&drvdata->csdev->dev, > "timeout while waiting for completion of Manual Flush\n"); > diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c > index 84ff4bf5d3b8..282d80e97265 100644 > --- a/drivers/hwtracing/coresight/coresight-tpiu.c > +++ b/drivers/hwtracing/coresight/coresight-tpiu.c > @@ -86,9 +86,9 @@ static void tpiu_disable_hw(struct csdev_access *csa) > /* Generate manual flush */ > csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR); > /* Wait for flush to complete */ > - coresight_timeout(csa->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); > + coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); > /* Wait for formatter to stop */ > - coresight_timeout(csa->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); > + coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); > > CS_LOCK(csa->base); > } > diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c > index 38e9c03ab754..21e7615fcbc8 100644 > --- a/drivers/hwtracing/coresight/coresight.c > +++ b/drivers/hwtracing/coresight/coresight.c > @@ -1338,23 +1338,26 @@ static void coresight_remove_conns(struct coresight_device *csdev) > } > > /** > - * coresight_timeout - loop until a bit has changed to a specific state. > - * @addr: base address of the area of interest. > - * @offset: address of a register, starting from @addr. > + * coresight_timeout - loop until a bit has changed to a specific register > + * state. > + * @csa: coresight device access for the device > + * @offset: Offset of the register from the base of the device. > * @position: the position of the bit of interest. > * @value: the value the bit should have. > * > * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if > * TIMEOUT_US has elapsed, which ever happens first. > */ > - > -int coresight_timeout(void __iomem *addr, u32 offset, int position, int value) > +int coresight_timeout(struct csdev_access *csa, > + u32 offset, > + int position, > + int value) > { > int i; > u32 val; > > for (i = TIMEOUT_US; i > 0; i--) { > - val = __raw_readl(addr + offset); > + val = csdev_access_read32(csa, offset); Here we are moving to a memory barrier access, which is probably not a bad thing. > /* waiting on the bit to go from 0 to 1 */ > if (value) { > if (val & BIT(position)) > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index 81ac708689f8..2989306f6041 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -433,8 +433,10 @@ coresight_register(struct coresight_desc *desc); > extern void coresight_unregister(struct coresight_device *csdev); > extern int coresight_enable(struct coresight_device *csdev); > extern void coresight_disable(struct coresight_device *csdev); > -extern int coresight_timeout(void __iomem *addr, u32 offset, > - int position, int value); > +extern int coresight_timeout(struct csdev_access *csa, > + u32 offset, > + int position, > + int value); > > extern int coresight_claim_device(void __iomem *base); > extern int coresight_claim_device_unlocked(void __iomem *base); > @@ -460,8 +462,15 @@ static inline void coresight_unregister(struct coresight_device *csdev) {} > static inline int > coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } > static inline void coresight_disable(struct coresight_device *csdev) {} > -static inline int coresight_timeout(void __iomem *addr, u32 offset, > - int position, int value) { return 1; } > + > +static inline int coresight_timeout(struct csdev_access *csa, > + u32 offset, > + int position, > + int value) > +{ > + return 1; > +} Reviewed-by: Mathieu Poirier > + > static inline int coresight_claim_device_unlocked(void __iomem *base) > { > return -EINVAL; > -- > 2.24.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel