From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62E14C433DF for ; Thu, 6 Aug 2020 12:02:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2EB9422D02 for ; Thu, 6 Aug 2020 12:02:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="U9LeCIbJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2EB9422D02 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=dmWgmcjDxKvH0vqM6ILrScT+xfzpjMKToVo+SPoSDyA=; b=U9LeCIbJtqZCEd1AKMinhPGsu +HSAmBeRNG3kySZdXhqxGSm3EqAqJKvd3D32RcIOxOm9P9LmhWefhK1FiEDBbNGy0f6qHKgMnMeO6 bt1i+C4olkZz8bRtWJOQn63rqBfXvLhdY9Nh6kUYXHeaCS3Pc4vyOOwiI3xAMFNmMcBbGZwlv7g5D Dc3loUZ39KHiETsJVCBSuqF+vxXshG82O0BpAD0xxWzDeu1wgOE6FBotMAqPECVUTZoZGuckdwwWf bKg9hNxfXbbGBBaPV/BLCR41wKzOELemPxs5QoKlk5eb+SF3j64dW929gZF7WcSmF6/6uKNaTkzAX fyFXk0U/Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k3eaI-0001lz-SN; Thu, 06 Aug 2020 12:01:22 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k3eaE-0001kh-Tb for linux-arm-kernel@lists.infradead.org; Thu, 06 Aug 2020 12:01:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D8001FB; Thu, 6 Aug 2020 05:01:13 -0700 (PDT) Received: from gaia (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1D4243F99C; Thu, 6 Aug 2020 05:01:12 -0700 (PDT) Date: Thu, 6 Aug 2020 13:01:09 +0100 From: Catalin Marinas To: Sami Tolvanen Subject: Re: [PATCH] arm64: tlb: fix ARM64_TLB_RANGE with LLVM's integrated assembler Message-ID: <20200806120109.GD23785@gaia> References: <20200805181920.4013059-1-samitolvanen@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200805181920.4013059-1-samitolvanen@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200806_080119_553503_623D9A58 X-CRM114-Status: GOOD ( 17.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Kees Cook , Zhenyu Ye , Marc Zyngier , Nick Desaulniers , linux-kernel@vger.kernel.org, clang-built-linux@googlegroups.com, Nathan Chancellor , Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 05, 2020 at 11:19:20AM -0700, Sami Tolvanen wrote: > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index d493174415db..66c2aab5e9cb 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -16,6 +16,16 @@ > #include > #include > > +/* > + * Enable ARMv8.4-TLBI instructions with ARM64_TLB_RANGE. Note that binutils > + * doesn't support .arch_extension tlb-rmi, so use .arch armv8.4-a instead. > + */ > +#ifdef CONFIG_ARM64_TLB_RANGE > +#define __TLBI_PREAMBLE ".arch armv8.4-a\n" > +#else > +#define __TLBI_PREAMBLE > +#endif > + > /* > * Raw TLBI operations. > * > @@ -28,14 +38,16 @@ > * not. The macros handles invoking the asm with or without the > * register argument as appropriate. > */ > -#define __TLBI_0(op, arg) asm ("tlbi " #op "\n" \ > +#define __TLBI_0(op, arg) asm (__TLBI_PREAMBLE \ > + "tlbi " #op "\n" \ > ALTERNATIVE("nop\n nop", \ > "dsb ish\n tlbi " #op, \ > ARM64_WORKAROUND_REPEAT_TLBI, \ > CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ > : : ) > > -#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0\n" \ > +#define __TLBI_1(op, arg) asm (__TLBI_PREAMBLE \ > + "tlbi " #op ", %0\n" \ > ALTERNATIVE("nop\n nop", \ > "dsb ish\n tlbi " #op ", %0", \ > ARM64_WORKAROUND_REPEAT_TLBI, \ A potential problem here is that for gas (not sure about the integrated assembler), .arch overrides any other .arch. So if we end up with two preambles included in the same generated .S files in the future, it will lead to some random behaviour. Does the LLVM integrated assembler have the same behaviour on .arch overriding a prior .arch? Maybe a better solution is for all inline asm on arm64 to have a standard preamble which is the maximum supported architecture version. We can add individual .arch_extension as those are not overriding. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel