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Mon, 10 Aug 2020 05:54:33 -0700 (PDT) Date: Mon, 10 Aug 2020 14:54:32 +0200 From: Daniel Vetter To: Linus Walleij Subject: Re: [PATCH 1/4 v2] drm/mcde: Improve pixel fetcher FIFO depth setting Message-ID: <20200810125432.GP2352366@phenom.ffwll.local> References: <20200808223122.1492124-1-linus.walleij@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200808223122.1492124-1-linus.walleij@linaro.org> X-Operating-System: Linux phenom 5.7.0-1-amd64 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200810_085437_437904_F1D3114C X-CRM114-Status: GOOD ( 28.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephan Gerhold , newbytee@protonmail.com, Maarten Lankhorst , Maxime Ripard , dri-devel@lists.freedesktop.org, Sean Paul , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Aug 09, 2020 at 12:31:19AM +0200, Linus Walleij wrote: > The pixel fetcher FIFO depth was just hardcoded to 48 > which works fine as long as the framebuffer is 32BPP > and the DSI output is RGB888. > > We will need more elaborate handling for some buffer > formats and displays, so start to improve this function > by setting reasonable defaults for 32, 24 and 16 BPP > framebuffers. > > Cc: newbytee@protonmail.com > Cc: Stephan Gerhold > Signed-off-by: Linus Walleij > --- > drivers/gpu/drm/mcde/mcde_display.c | 34 +++++++++++++++++++++++++---- > 1 file changed, 30 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/mcde/mcde_display.c b/drivers/gpu/drm/mcde/mcde_display.c > index cac660ac8803..cbc7c0c4955a 100644 > --- a/drivers/gpu/drm/mcde/mcde_display.c > +++ b/drivers/gpu/drm/mcde/mcde_display.c > @@ -333,7 +333,7 @@ static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl, > enum mcde_extsrc src, > enum mcde_channel ch, > const struct drm_display_mode *mode, > - u32 format) > + u32 format, int cpp) Note that format->cpp is a bit outdated, since it doesn't work for planar stuff. But I guess not a problem for you (for now at least). Blocky formats like yuv don't set format->cpp, or at least not in the way you'd expect. Anyway now idea on the hw, but patch looks reasonable. Acked-by: Daniel Vetter > { > u32 val; > u32 conf1; > @@ -342,6 +342,7 @@ static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl, > u32 ljinc; > u32 cr; > u32 comp; > + u32 pixel_fetcher_watermark; > > switch (ovl) { > case MCDE_OVERLAY_0: > @@ -426,8 +427,33 @@ static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl, > format); > break; > } > - /* The default watermark level for overlay 0 is 48 */ > - val |= 48 << MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT; > + > + /* > + * Pixel fetch watermark level is max 0x1FFF pixels. > + * Two basic rules should be followed: > + * 1. The value should be at least 256 bits. > + * 2. The sum of all active overlays pixelfetch watermark level > + * multiplied with bits per pixel, should be lower than the > + * size of input_fifo_size in bits. > + * 3. The value should be a multiple of a line (256 bits). > + */ > + switch (cpp) { > + case 2: > + pixel_fetcher_watermark = 128; > + break; > + case 3: > + pixel_fetcher_watermark = 96; > + break; > + case 4: > + pixel_fetcher_watermark = 48; > + break; > + default: > + pixel_fetcher_watermark = 48; > + break; > + } > + dev_dbg(mcde->dev, "pixel fetcher watermark level %d pixels\n", > + pixel_fetcher_watermark); > + val |= pixel_fetcher_watermark << MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT; > writel(val, mcde->regs + conf2); > > /* Number of bytes to fetch per line */ > @@ -932,7 +958,7 @@ static void mcde_display_enable(struct drm_simple_display_pipe *pipe, > * channel 0 > */ > mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0, > - MCDE_CHANNEL_0, mode, format); > + MCDE_CHANNEL_0, mode, format, cpp); > > /* > * Configure pixel-per-line and line-per-frame for channel 0 and then > -- > 2.26.2 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel