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Mon, 17 Aug 2020 16:53:06 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id D175EC433C6; Mon, 17 Aug 2020 16:53:05 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1C653C433C6; Mon, 17 Aug 2020 16:53:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1C653C433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Mon, 17 Aug 2020 10:52:59 -0600 From: Jordan Crouse To: Rob Clark Subject: Re: [Freedreno] [PATCH 05/19] iommu: add private interface for adreno-smmu Message-ID: <20200817165259.GH3221@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Rob Clark , dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , Joerg Roedel , Robin Murphy , Bjorn Andersson , Sibi Sankar , Vivek Gautam , Stephen Boyd , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-6-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-6-robdclark@gmail.com> User-Agent: Mutt/1.5.24 (2015-08-30) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_125340_719472_D9C28653 X-CRM114-Status: GOOD ( 31.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , freedreno@lists.freedesktop.org, Sai Prakash Ranjan , linux-arm-msm@vger.kernel.org, Joerg Roedel , open list , dri-devel@lists.freedesktop.org, Bjorn Andersson , iommu@lists.linux-foundation.org, Sibi Sankar , Vivek Gautam , Stephen Boyd , Will Deacon , linux-arm-kernel@lists.infradead.org, Robin Murphy Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 13, 2020 at 07:41:00PM -0700, Rob Clark wrote: > From: Rob Clark > > This interface will be used for drm/msm to coordinate with the > qcom_adreno_smmu_impl to enable/disable TTBR0 translation. > > Once TTBR0 translation is enabled, the GPU's CP (Command Processor) > will directly switch TTBR0 pgtables (and do the necessary TLB inv) > synchronized to the GPU's operation. But help from the SMMU driver > is needed to initially bootstrap TTBR0 translation, which cannot be > done from the GPU. > > Since this is a very special case, a private interface is used to > avoid adding highly driver specific things to the public iommu > interface. > Reviewed-by: Jordan Crouse > Signed-off-by: Rob Clark > --- > include/linux/adreno-smmu-priv.h | 36 ++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 include/linux/adreno-smmu-priv.h > > diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h > new file mode 100644 > index 000000000000..a889f28afb42 > --- /dev/null > +++ b/include/linux/adreno-smmu-priv.h > @@ -0,0 +1,36 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2020 Google, Inc > + */ > + > +#ifndef __ADRENO_SMMU_PRIV_H > +#define __ADRENO_SMMU_PRIV_H > + > +#include > + > +/** > + * struct adreno_smmu_priv - private interface between adreno-smmu and GPU > + * > + * @cookie: An opque token provided by adreno-smmu and passed > + * back into the callbacks > + * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank > + * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A > + * NULL config disables TTBR0 translation, otherwise > + * TTBR0 translation is enabled with the specified cfg > + * > + * The GPU driver (drm/msm) and adreno-smmu work together for controlling > + * the GPU's SMMU instance. This is by necessity, as the GPU is directly > + * updating the SMMU for context switches, while on the other hand we do > + * not want to duplicate all of the initial setup logic from arm-smmu. > + * > + * This private interface is used for the two drivers to coordinate. The > + * cookie and callback functions are populated when the GPU driver attaches > + * it's domain. > + */ > +struct adreno_smmu_priv { > + const void *cookie; > + const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); > + int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); > +}; > + > +#endif /* __ADRENO_SMMU_PRIV_H */ > \ No newline at end of file > -- > 2.26.2 > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel