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Thu, 20 Aug 2020 14:03:34 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 20 Aug 2020 14:03:33 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 20 Aug 2020 14:03:33 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07KJ3XgB073160; Thu, 20 Aug 2020 14:03:33 -0500 Date: Thu, 20 Aug 2020 14:03:33 -0500 From: Nishanth Menon To: Suman Anna Subject: Re: [PATCH 2/7] arm64: dts: ti: k3-j721e-common-proc-board: Add mailboxes to C66x DSPs Message-ID: <20200820190333.4ga5uob5tgsgwego@akan> References: <20200820010331.2911-1-s-anna@ti.com> <20200820010331.2911-3-s-anna@ti.com> <20200820114238.7ovvxq5n3fogzowi@akan> <8491a1bf-3665-8f23-6b75-34890566fcae@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <8491a1bf-3665-8f23-6b75-34890566fcae@ti.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200820_150336_228207_CB7E0286 X-CRM114-Status: GOOD ( 16.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tero Kristo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 08:25-20200820, Suman Anna wrote: [...] > > I am just wondering if the carveouts and mbox linkage should be in the > > common processor board? if that makes sense at all? I know we already > > have other definitions.. Trying to see if we are making it harder to > > understand the definition than that is necessary.. > > In general, I consider these as stuff that needs to be added to the board dts > files. You will see that this is what I have followed on all the TI > AM57xx/DRA7xx boards. For J721E, we have a weird organization as the memory > node, typically a board property, is defined in the som dtsi file, so the > reserved memory nodes are also added in the som dtsi file. The convention I > followed in general is to have the reserved-memory and memory nodes together. > > If you think the mailbox nodes should be moved into the SoM dts file, I could do I think that might make more sense and less confusing. I'd rather leave the processor board dts for more signal and interface hookup related topics as it is done right now. if we do endup with too many SoM duplication, then we should consider it's own dtsi > it as a follow-on cleanup series, but would wait for the ABI 3.0 changes to be > merged first. Of course. We are expecting this to be part of rc2, please rebase and post once the tag is out. next-20200820 has it already, if you want a pre-look. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel