From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CFA9C433E3 for ; Fri, 21 Aug 2020 12:28:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 282CF20724 for ; Fri, 21 Aug 2020 12:28:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="pj4PLWLb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 282CF20724 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=thC6/TPbFq+MrTpJEzNDKw7UNRfKmAPwj9U4H8hN+CY=; b=pj4PLWLb9rbFkvrrDcseH+3lX e8o+BYfrRF3GXYeoOZ3wV77YjV9ld0T8pYk8o2oFdLFWNt3YKasSQDdllgAyPYqaWK65pcNlnSFkG B1oX+fcWe6MGQo4ueiBa2TRN+B++GuYEMf98rMNhZQOdH77FXJqNsOWHQyx3l12dAkYl0aHEuCWJ1 Q4lDtck8++f5Dw/IrxFsjpR8saNwuwhQYLvxY8WZMJNA2ND4FZiN1EmYAmYPwLA8v17s3p/6lgBp2 txzPn02fpNBJ5z/0W7KMNfeQnxB1Q+svAfG3fWK3KoTsb6IVan6trLeKDH0NLlS4/VJuQXIXQpwBD 2dHvvEMoA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k9680-00088e-Q7; Fri, 21 Aug 2020 12:26:40 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k967y-00088D-DK for linux-arm-kernel@lists.infradead.org; Fri, 21 Aug 2020 12:26:39 +0000 Received: from gaia (unknown [95.146.230.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E1F6E20724; Fri, 21 Aug 2020 12:26:35 +0000 (UTC) Date: Fri, 21 Aug 2020 13:26:33 +0100 From: Catalin Marinas To: Will Deacon Subject: Re: [PATCH v4 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412 Message-ID: <20200821122633.GC6823@gaia> References: <20200803193127.3012242-1-robh@kernel.org> <20200803193127.3012242-4-robh@kernel.org> <20200821120659.GB6823@gaia> <20200821121209.GB20833@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200821121209.GB20833@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200821_082638_524020_F2CAFEB0 X-CRM114-Status: GOOD ( 17.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Suzuki K Poulose , Marc Zyngier , James Morse , Andrew Scull , Julien Thierry , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 21, 2020 at 01:12:10PM +0100, Will Deacon wrote: > On Fri, Aug 21, 2020 at 01:07:00PM +0100, Catalin Marinas wrote: > > On Mon, Aug 03, 2020 at 01:31:27PM -0600, Rob Herring wrote: > > > @@ -979,6 +980,14 @@ > > > write_sysreg(__scs_new, sysreg); \ > > > } while (0) > > > > > > +#define read_sysreg_par() ({ \ > > > + u64 par; \ > > > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ > > > + par = read_sysreg(par_el1); \ > > > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ > > > + par; \ > > > +}) > > > > I was about to queue this up but one more point to clarify: can we get > > an interrupt at either side of the PAR_EL1 read and the handler do a > > device read, triggering the erratum? Do we need a DMB at exception > > entry/return? > > Disabling irqs around the PAR access would be simpler, I think (assuming > this is needed). This wouldn't work if it interrupts a guest. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel