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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAUcb-0000fs-3u; Tue, 25 Aug 2020 08:48:01 +0000 Received: from relay5-d.mail.gandi.net ([217.70.183.197]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAUcY-0000eq-AU for linux-arm-kernel@lists.infradead.org; Tue, 25 Aug 2020 08:47:59 +0000 X-Originating-IP: 90.66.108.79 Received: from localhost (lfbn-lyo-1-1932-79.w90-66.abo.wanadoo.fr [90.66.108.79]) (Authenticated sender: alexandre.belloni@bootlin.com) by relay5-d.mail.gandi.net (Postfix) with ESMTPSA id 2CD061C0011; Tue, 25 Aug 2020 08:47:53 +0000 (UTC) Date: Tue, 25 Aug 2020 10:47:52 +0200 From: Alexandre Belloni To: Ulf Hansson Subject: Re: [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings Message-ID: <20200825084752.GD2389103@piout.net> References: <20200824151035.31093-1-lars.povlsen@microchip.com> <20200824151035.31093-2-lars.povlsen@microchip.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200825_044758_548596_EB7F0815 X-CRM114-Status: GOOD ( 23.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , List-Id: Cc: DTML , Linux Kernel Mailing List , "linux-mmc@vger.kernel.org" , Adrian Hunter , Microchip Linux Driver Support , SoC Team , Rob Herring , Linux ARM , Lars Povlsen Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 25/08/2020 09:33:45+0200, Ulf Hansson wrote: > On Mon, 24 Aug 2020 at 17:10, Lars Povlsen wrote: > > > > The Sparx5 SDHCI controller is based on the Designware controller IP. > > > > Signed-off-by: Lars Povlsen > > --- > > .../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++++++++++++++++ > > 1 file changed, 65 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml > > > > diff --git a/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml > > new file mode 100644 > > index 0000000000000..55883290543b9 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml > > @@ -0,0 +1,65 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Microchip Sparx5 Mobile Storage Host Controller Binding > > + > > +allOf: > > + - $ref: "mmc-controller.yaml" > > + > > +maintainers: > > + - Lars Povlsen > > + > > +# Everything else is described in the common file > > +properties: > > + compatible: > > + const: microchip,dw-sparx5-sdhci > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + description: > > + Handle to "core" clock for the sdhci controller. > > + > > + clock-names: > > + items: > > + - const: core > > + > > + microchip,clock-delay: > > + description: Delay clock to card to meet setup time requirements. > > + Each step increase by 1.25ns. > > + $ref: "/schemas/types.yaml#/definitions/uint32" > > + minimum: 1 > > + maximum: 15 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + > > +examples: > > + - | > > + #include > > + #include > > + sdhci0: mmc@600800000 { > > Nitpick: > > I think we should use solely "mmc[n]" here. So: > > mmc0@600800000 { > > Please update patch3/3 accordingly as well. This is not what the devicetree specification says. 2.2.2 says that the generic name is mmc, not mmc[n]. Since there is a proper unit-address, I don't see the need for an index here. > > > + compatible = "microchip,dw-sparx5-sdhci"; > > + reg = <0x00800000 0x1000>; > > + pinctrl-0 = <&emmc_pins>; > > + pinctrl-names = "default"; > > + clocks = <&clks CLK_ID_AUX1>; > > + clock-names = "core"; > > + assigned-clocks = <&clks CLK_ID_AUX1>; > > + assigned-clock-rates = <800000000>; > > + interrupts = ; > > + bus-width = <8>; > > + microchip,clock-delay = <10>; > > + }; > > Kind regards > Uffe -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel