From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 569E5C433DF for ; Tue, 25 Aug 2020 19:10:57 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 29AA22074D for ; Tue, 25 Aug 2020 19:10:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="yT136BZp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 29AA22074D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=PTWNxfQBU/4yEft+GMm3sqlPWkS3v3A46OqPNqASA/s=; b=yT136BZpDtIc5gRjTwrlNVGdv yyyL90xRuslnCopk3dMp4b9DnEvnHnOt9qZvrB8DhdZUDsYmzhYCaWKkL5bVtIoEQmYZD38KLaI07 vgzMDhv7O6Ef8cezirzNi350xLW1T5tMlpjFCBHWLFgO383N0C1QMfZ1sI9+Da1htSozW+CY54O3Q geVRVJvm4zANpWO6y+o6tWAWlN2PV29s7uDTHpFHgL6Mjqvy/rumRLoq1LRHcxzqgHhw0AB8ZEfpj c938CUy+Qn//GlPWjkTuyebch7iTxSWtlhJtzb0reb9PBUwspMYBHPdO+q9tHUq/a8wxjg0OjiJB8 4fSODa2Cw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAeK2-00040u-9g; Tue, 25 Aug 2020 19:09:30 +0000 Received: from mail-io1-f67.google.com ([209.85.166.67]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAeK0-0003zy-B7 for linux-arm-kernel@lists.infradead.org; Tue, 25 Aug 2020 19:09:29 +0000 Received: by mail-io1-f67.google.com with SMTP id g13so13638336ioo.9 for ; Tue, 25 Aug 2020 12:09:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=eEnscZ144fB/Icib0BxejX+dHld9Sfy5N1mdgz0fLTI=; b=sbCnE1V+o1XAGKuBEXEU29gPbnCL+yOkzGFN2bFBthoEWZn7XJhPJtXe+fqnXPJ5m6 SSAWxyr6p6iFJrShhTfjcZ/bGlIa/ubmhSAhrjoOadcLPYm/RzohQuzahB4ZG2QcJSB3 IFOlbnNLL72ysw5DVZIZEjKPLRo+rW76HaiXv8tZUKDFjzYl854WM3aZHbis5dSt5ZJR Cuq3Fa/cQHyI5f31qYuV0nfV1yVxe7NT9osrEAjElECMKcVkG6VDRXIr4+ukihD9apY9 QL5W2sTmRWMMPSiHpG1DR/uDcCZAPx8DA34151zid2QxqGmM8gCYzewc8/V6oMGZcsXh c3yw== X-Gm-Message-State: AOAM531sWO/YUUjZ2nrMLTconikDACk1JJJDJabLU60BmJjkHuHvjNmZ oU1RLZQmLuew6AF+CS2xKsLaokcmZmhw X-Google-Smtp-Source: ABdhPJyG8THBO7xd0t/WMwBcD/ftApc9n5G5bBZV+A53FZSw7DcNoHRLyBUu6gbhqznyE9MRd5K6EA== X-Received: by 2002:a05:6602:2106:: with SMTP id x6mr9859814iox.84.1598382567254; Tue, 25 Aug 2020 12:09:27 -0700 (PDT) Received: from xps15 ([64.188.179.249]) by smtp.gmail.com with ESMTPSA id o62sm9717855ilb.38.2020.08.25.12.09.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 12:09:26 -0700 (PDT) Received: (nullmailer pid 1144568 invoked by uid 1000); Tue, 25 Aug 2020 19:09:21 -0000 Date: Tue, 25 Aug 2020 13:09:21 -0600 From: Rob Herring To: Grzegorz Jaszczyk Subject: Re: [PATCH v5 1/5] dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings Message-ID: <20200825190921.GA1144515@bogus> References: <1597671613-20879-1-git-send-email-grzegorz.jaszczyk@linaro.org> <1597671613-20879-2-git-send-email-grzegorz.jaszczyk@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1597671613-20879-2-git-send-email-grzegorz.jaszczyk@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200825_150928_397089_CA6A514F X-CRM114-Status: GOOD ( 20.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Roger Quadros , linux-omap@vger.kernel.org, jason@lakedaemon.net, praneeth@ti.com, maz@kernel.org, linux-kernel@vger.kernel.org, "Andrew F . Davis" , robh+dt@kernel.org, tglx@linutronix.de, lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 17 Aug 2020 15:40:09 +0200, Grzegorz Jaszczyk wrote: > From: Suman Anna > > The Programmable Real-Time Unit and Industrial Communication Subsystem > (PRU-ICSS or simply PRUSS) contains an interrupt controller (INTC) that > can handle various system input events and post interrupts back to the > device-level initiators. The INTC can support up to 64 input events on > most SoCs with individual control configuration and h/w prioritization. > These events are mapped onto 10 output interrupt lines through two levels > of many-to-one mapping support. Different interrupt lines are routed to > the individual PRU cores or to the host CPU or to other PRUSS instances. > > The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, > commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide > a higher number of host interrupts (20 vs 10) and can handle an increased > number of input events (160 vs 64) from various SoC interrupt sources. > > Add the bindings document for these interrupt controllers on all the > applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x > and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci > architecture based OMAPL138 SoCs, and the K3 architecture based AM65x > and J721E SoCs. > > Signed-off-by: Suman Anna > Signed-off-by: Andrew F. Davis > Signed-off-by: Roger Quadros > Signed-off-by: Grzegorz Jaszczyk > --- > v4->v5: > - Fix typo in commit description. > - Update interrupt-cells description regarding each cells meaning. > v3->v4: > - Drop allOf references to interrupt-controller.yaml and > interrupts.yaml. > - Drop items descriptions and use only maxItems: 1 as suggested by Rob. > - Convert irqs-reserved property from uint8-array to bitmask. > - Minor descriptions updates. > - Change interrupt-cells to 3 in order to provide 2-level mapping > description for interrupts routed to the main CPU (as Marc requested). > - Merge the irqs-reserved and irqs-shared to one property since they > can be handled by one logic. > - Drop reviewed-by due to introduced changes. > - Add another example illustrating irqs-reserved property usage. > v2->v3: > - Convert dt-binding to YAML > v1->v2: > - https://patchwork.kernel.org/patch/11069767/ > > update irq-pruss-intc binding > --- > .../interrupt-controller/ti,pruss-intc.yaml | 158 +++++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml > Reviewed-by: Rob Herring _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel