[PATCH] clk: imx: fix composite peripheral flags

From: peng.fan@nxp.com
To: sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de
Cc: Peng Fan <peng.fan@nxp.com>,
	abel.vesa@nxp.com, Anson.Huang@nxp.com,
	linux-kernel@vger.kernel.org, linux-imx@nxp.com,
	kernel@pengutronix.de, festevam@gmail.com,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH] clk: imx: fix composite peripheral flags
Date: Wed, 26 Aug 2020 15:14:07 +0800	[thread overview]
Message-ID: <20200826071407.10543-1-peng.fan@nxp.com> (raw)

From: Peng Fan <peng.fan@nxp.com>

According to RM, for peripheral clock slice,
"IP clock slices must be stopped to change the clock source.".

So we must have CLK_SET_PARENT_GATE flag to avoid glitch.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-8m.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 78fb7e52a42a..2c309e3dc8e3 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -216,6 +216,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 		div->width = PCG_PREDIV_WIDTH;
 		divider_ops = &imx8m_clk_composite_divider_ops;
 		mux_ops = &clk_mux_ops;
+		flags |= CLK_SET_PARENT_GATE;
 	}
 
 	div->lock = &imx_ccm_lock;
-- 
2.28.0


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