From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BD28C433E1 for ; Wed, 26 Aug 2020 15:25:57 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C47B12075E for ; Wed, 26 Aug 2020 15:25:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="jR+UwvEZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C47B12075E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xk4AN9UEamWSvX0+bw8xLVJvY8cD4W0trnQitwx0FbU=; b=jR+UwvEZXB5V7OkLt9iKaa9+9 bRSb6/QZoalapuxsgYJnynC+IgbEbjbcRK2qLz/AarLRlr/mg6jtxK1/WoUzuXo1Fn0+8jm2PBz+H 9aIxlG9vggQ4HKyaPKr5n43AR/O99to8HxGoZDEIADc9owuzuPqteF0+4AlvOgSmUBRuduQcaz43R KiW/xXmQ3EqUTa3O4f71vGez9AL56Ed9tLOm+VuyC9Fw3ibDi6eS1sIeTxr4HEKRWmNOj7aOPopXx pQjdJP8CnH88nNcTC764NaJyau7NUnWZ1mxUz7h921GAy9HOcJQF6h80iEl9gfu3DG8UQYE6pjkz2 rys6GRS2A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAxHg-0004BY-Mj; Wed, 26 Aug 2020 15:24:21 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kAxHd-0004Am-Vg for linux-arm-kernel@lists.infradead.org; Wed, 26 Aug 2020 15:24:18 +0000 Received: from gaia (unknown [46.69.195.127]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8A3D82075E; Wed, 26 Aug 2020 15:24:14 +0000 (UTC) Date: Wed, 26 Aug 2020 16:24:12 +0100 From: Catalin Marinas To: Marc Zyngier Subject: Re: [PATCH v8 03/28] arm64: mte: CPU feature detection and initial sysreg configuration Message-ID: <20200826152411.GA24545@gaia> References: <20200824182758.27267-1-catalin.marinas@arm.com> <20200824182758.27267-4-catalin.marinas@arm.com> <61bba3c1948651a5221b87f2dfa2872f@kernel.org> <20200825105450.GA22233@C02TF0J2HF1T.local> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200825105450.GA22233@C02TF0J2HF1T.local> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200826_112418_092231_41D80161 X-CRM114-Status: GOOD ( 23.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Suzuki K Poulose , Szabolcs Nagy , Andrey Konovalov , Kevin Brodsky , Peter Collingbourne , linux-mm@kvack.org, Andrew Morton , Vincenzo Frascino , Will Deacon , Dave P Martin , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Aug 25, 2020 at 11:54:50AM +0100, Catalin Marinas wrote: > On Tue, Aug 25, 2020 at 09:53:16AM +0100, Marc Zyngier wrote: > > On 2020-08-24 19:27, Catalin Marinas wrote: > > > diff --git a/arch/arm64/include/asm/kvm_arm.h > > > b/arch/arm64/include/asm/kvm_arm.h > > > index 8a1cbfd544d6..6c3b2fc922bb 100644 > > > --- a/arch/arm64/include/asm/kvm_arm.h > > > +++ b/arch/arm64/include/asm/kvm_arm.h > > > @@ -78,7 +78,7 @@ > > > HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ > > > HCR_FMO | HCR_IMO) > > > #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) > > > -#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK) > > > +#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) > > > #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) > > > > Why is HCR_ATA only set for nVHE? HCR_EL2.ATA seems to apply to both, > > doesn't it? > > We need HCR_EL2.ATA to be set when !VHE so that the host kernel can use > MTE. That said, I think we need to turn it off when running a guest. > Even if we hide the ID register, the guest may still attempt to enable > tags on some memory that doesn't support it, leading to unpredictable > behaviour (well, only if we expose device memory to guests directly; > Steve's patches will deal with this but for now we just disable MTE in > guests). So if we want to properly disable MTE for guests when !VHE (not just the ID reg), I came up with the diff below. However, given that Steven is already working on KVM support, I wonder whether we could just make MTE depend on !VHE temporarily, remove it once we get the full MTE KVM support. It's up to you (either way, I still need to solve the undef injection since that affects both VHE and !VHE; patch to follow). diff --git a/arch/arm64/kvm/hyp/nvhe/tlb.c b/arch/arm64/kvm/hyp/nvhe/tlb.c index 69eae608d670..51204ac30154 100644 --- a/arch/arm64/kvm/hyp/nvhe/tlb.c +++ b/arch/arm64/kvm/hyp/nvhe/tlb.c @@ -32,10 +32,23 @@ static void __tlb_switch_to_guest(struct kvm_s2_mmu *mmu, } __load_guest_stage2(mmu); + + /* MTE is not supported in guests yet, disable access to tags */ + if (system_supports_mte()) { + u64 val = read_sysreg(hcr_el2); + val &= ~HCR_ATA; + write_sysreg(val, hcr_el2); + } } static void __tlb_switch_to_host(struct tlb_inv_context *cxt) { + /* Re-enable MTE for the host kernel */ + if (system_supports_mte()) { + u64 val = read_sysreg(hcr_el2); + write_sysreg(val | HCR_ATA, hcr_el2); + } + write_sysreg(0, vttbr_el2); if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel