From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B492BC433E3 for ; Thu, 27 Aug 2020 11:15:06 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7DA0522CF6 for ; Thu, 27 Aug 2020 11:15:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ElNG+3pV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7DA0522CF6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=e9YTUlDU/nEU9ClCv9DRZ/0lVHHu9QkUtZSuUTAzzZI=; b=ElNG+3pVknV9xceOZNVUu9Tgt LfI33gjWuZH1eEsuIvxN+LltwC2jZ7iQBCmyPfkgENZxWwY9AFH8kBMvzZAiaXSGAFvhxmc+zRzUn Pg9oOELeVAeF04+24xbX1/43lNptVEEplIAW4eUV4tgtFeXyW8F0uvLYu8q8+ktX0bFjgPKNQ+ynF VmFSNWboK9ZrZWhC2cIs0d54qWLvD+pTEgJIjjK6IBNzvpC274sX3HLRlwn0HdX9l6Y21HzBKEDrh LO679aIABTn79AhmMR3c0yF9Bs0/Z/EMvKs+c5YkDIwsqptvu3FcWCGsQTKnm9sfCpm4vpiLvlJ4X irfpHKBNg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBFqs-00041U-0d; Thu, 27 Aug 2020 11:13:54 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBFqo-000402-UV for linux-arm-kernel@lists.infradead.org; Thu, 27 Aug 2020 11:13:51 +0000 Received: from gaia (unknown [46.69.195.127]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 867CA22CB3; Thu, 27 Aug 2020 11:13:47 +0000 (UTC) Date: Thu, 27 Aug 2020 12:13:45 +0100 From: Catalin Marinas To: Vincenzo Frascino Subject: Re: [PATCH 26/35] kasan, arm64: Enable TBI EL1 Message-ID: <20200827111344.GK29264@gaia> References: <518da1e5169a4e343caa3c37feed5ad551b77a34.1597425745.git.andreyknvl@google.com> <20200827104033.GF29264@gaia> <9c53dfaa-119e-b12e-1a91-1f67f4aef503@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <9c53dfaa-119e-b12e-1a91-1f67f4aef503@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200827_071351_085219_04FEDB06 X-CRM114-Status: GOOD ( 18.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Marco Elver , Elena Petrova , Andrey Konovalov , Kevin Brodsky , Will Deacon , Branislav Rankov , kasan-dev@googlegroups.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexander Potapenko , Evgenii Stepanov , Andrey Ryabinin , Andrew Morton , Dmitry Vyukov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 27, 2020 at 12:05:55PM +0100, Vincenzo Frascino wrote: > On 8/27/20 11:40 AM, Catalin Marinas wrote: > > On Fri, Aug 14, 2020 at 07:27:08PM +0200, Andrey Konovalov wrote: > >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > >> index 152d74f2cc9c..6880ddaa5144 100644 > >> --- a/arch/arm64/mm/proc.S > >> +++ b/arch/arm64/mm/proc.S > >> @@ -38,7 +38,7 @@ > >> /* PTWs cacheable, inner/outer WBWA */ > >> #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA > >> > >> -#ifdef CONFIG_KASAN_SW_TAGS > >> +#if defined(CONFIG_KASAN_SW_TAGS) || defined(CONFIG_KASAN_HW_TAGS) > >> #define TCR_KASAN_FLAGS TCR_TBI1 > >> #else > >> #define TCR_KASAN_FLAGS 0 > > > > I prefer to turn TBI1 on only if MTE is present. So on top of the v8 > > user series, just do this in __cpu_setup. > > Not sure I understand... Enabling TBI1 only if MTE is present would break > KASAN_SW_TAGS which is based on TBI1 but not on MTE. You keep the KASAN_SW_TAGS as above but for HW_TAGS, only set TBI1 later in __cpu_setup(). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel