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Mon, 31 Aug 2020 22:31:48 -0700 (PDT) Date: Tue, 1 Sep 2020 00:31:45 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 18/19] iommu/arm-smmu: add a way for implementations to influence SCTLR Message-ID: <20200901053145.GX3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-19-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-19-robdclark@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_013151_304521_78265667 X-CRM114-Status: GOOD ( 21.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , Jordan Crouse , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Sibi Sankar , Vivek Gautam , Greg Kroah-Hartman , Jon Hunter , Thierry Reding , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Rob Clark > > For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that > pending translations are not terminated on iova fault. Otherwise > a terminated CP read could hang the GPU by returning invalid > command-stream data. > Reviewed-by: Bjorn Andersson > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++ > 3 files changed, 12 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index 5640d9960610..2aa6249050ff 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -127,6 +127,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > + /* > + * On the GPU device we want to process subsequent transactions after a > + * fault to keep the GPU from hanging > + */ > + smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF; > + > /* > * Initialize private interface with GPU: > */ > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c > index e63a480d7f71..bbec5793faf8 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c > @@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) > if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) > reg |= ARM_SMMU_SCTLR_E; > > + reg |= cfg->sctlr_set; > + reg &= ~cfg->sctlr_clr; > + > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); > } > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index cd75a33967bb..2df3a70a8a41 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -144,6 +144,7 @@ enum arm_smmu_cbar_type { > #define ARM_SMMU_CB_SCTLR 0x0 > #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) > #define ARM_SMMU_SCTLR_CFCFG BIT(7) > +#define ARM_SMMU_SCTLR_HUPCF BIT(8) > #define ARM_SMMU_SCTLR_CFIE BIT(6) > #define ARM_SMMU_SCTLR_CFRE BIT(5) > #define ARM_SMMU_SCTLR_E BIT(4) > @@ -341,6 +342,8 @@ struct arm_smmu_cfg { > u16 asid; > u16 vmid; > }; > + u32 sctlr_set; /* extra bits to set in SCTLR */ > + u32 sctlr_clr; /* bits to mask in SCTLR */ > enum arm_smmu_cbar_type cbar; > enum arm_smmu_context_fmt fmt; > }; > -- > 2.26.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel