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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id b10sm3737260pff.85.2020.09.03.10.42.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 10:42:46 -0700 (PDT) Date: Thu, 3 Sep 2020 11:42:45 -0600 From: Mathieu Poirier To: Jonathan Zhou Subject: Re: [PATCH] coresight: etm4x: fix issues on trcseqevr access Message-ID: <20200903174245.GC312784@xps15> References: <1599043033-57852-1-git-send-email-jonathan.zhouwen@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1599043033-57852-1-git-send-email-jonathan.zhouwen@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200903_134250_550730_DDD03659 X-CRM114-Status: GOOD ( 18.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shaokun Zhang , lizixian@hisilicon.com, Mike Leach , linux-arm-kernel@lists.infradead.org, Suzuki K Poulose Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 02, 2020 at 06:37:13PM +0800, Jonathan Zhou wrote: > The TRCSEQEVR(3) is reserved, using '@nrseqstate - 1' instead to avoid > accessing the reserved register. > > Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") > Cc: Mathieu Poirier > Cc: Suzuki K Poulose > Cc: Mike Leach > Cc: Shaokun Zhang > Cc: lizixian@hisilicon.com > > Signed-off-by: Jonathan Zhou > --- > drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 96425e818fc2..44e44c817bf8 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -1183,7 +1183,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR); > state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR); > > - for (i = 0; i < drvdata->nrseqstate; i++) > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i)); The section 3.4.3 "Guidelines for trace unit registers to be saved and restored" of the ETM4 Architecture Specification (ARM IHI0064F ID042818) is clear on the fact that registers TRCSEQEVR0-3 have to be taken into account when saving the trace unit state. Thanks, Mathieu > > state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR); > @@ -1288,7 +1288,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) > writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR); > writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR); > > - for (i = 0; i < drvdata->nrseqstate; i++) > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > writel_relaxed(state->trcseqevr[i], > drvdata->base + TRCSEQEVRn(i)); > -- > 1.9.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel