From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C200C433E2 for ; Mon, 7 Sep 2020 17:08:15 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4818F206B8 for ; Mon, 7 Sep 2020 17:08:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="k8F/GMkc"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="ps0piQnT" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4818F206B8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vAJdgwJLK0SiD6MSZe73Wv2uxDcN8jlLv7MCBz0H3SE=; b=k8F/GMkcyOEDRf6yFy9MgDSbQ qTX4kpNUQ+vM+7e4Z2+PUn/2UprYYlhWpeRYq2uw25bXZc/PTqTiO6IhlWHQnaUpzFyhV/Ic87zTM b8bA8Yoeea3jgwaF+GOEB13BhxxDmF8eJsSemU/ip8tZkEJsapOafKiFnEuxEGXLZiUBuxHJexm33 nyMBvzYSG5kCYPdypxqpXdxIygafaKyuIaN88KZhCHk+FcKPT1x79Z9NElHEF02QM6q8SHsADpiAq Cz8gSLm6AknOh7Yr/0l1uQAr5DIDtyYp/uTYT5AWxOjUIFHiDfl1aEZ/oNk9Et3/6UMRERl7pgl8m 3XNCkcDEw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFKbb-0005Y8-Va; Mon, 07 Sep 2020 17:07:00 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFKbZ-0005Xl-KQ for linux-arm-kernel@lists.infradead.org; Mon, 07 Sep 2020 17:06:58 +0000 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A83FF2080A; Mon, 7 Sep 2020 17:06:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1599498416; bh=M2Nv0XXHGiruwlX+RpUf4ClSPWY5ciRT5A3z92sX+VI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ps0piQnTGGbr8B7MHG/HyDwmdJEQg9KcId6G/aqWqUBQbqyfdAL4zEhzRNkEI9Qi6 yVQ5nYIfJLbiCdybhI5elsmB52hkIDPPCHfRpZtYuy3uQTGjyEvSAlYc3wwtYrtiNg eEWN8YKt70eh5VoiQiJyBfl2VUqnt6kjBIwk1naw= Date: Mon, 7 Sep 2020 18:06:52 +0100 From: Will Deacon To: Joakim Zhang Subject: Re: [PATCH] perf/imx_ddr: Add stop event counters support for i.MX8MP Message-ID: <20200907170651.GA13281@willie-the-truck> References: <1599472439-22770-1-git-send-email-qiangqing.zhang@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1599472439-22770-1-git-send-email-qiangqing.zhang@nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200907_130657_837266_8DBCAE05 X-CRM114-Status: GOOD ( 23.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, robin.murphy@arm.com, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Sep 07, 2020 at 05:53:59PM +0800, Joakim Zhang wrote: > DDR Perf driver only supports free-running event counters(counter1/2/3) > now, this patch adds support for stop event counters. > > Legacy SoCs: > Cycle counter(counter0) is a special counter, only count cycles. When > cycle counter overflow, it will lock all counters and generate an > interrupt. In ddr_perf_irq_handler, disable cycle counter then all > counters would stop at the same time, update all counters' count, then > enable cycle counter that all counters count again. During this process, > only clear cycle counter, no need to clear event counters since they are > free-running counters. They would continue counting after overflow and > do/while loop from ddr_perf_event_update can handle event counters > overflow case. > > i.MX8MP: > Almost all is the same as legacy SoCs, the only difference is that, event > counters are not free-running any more. Like cycle counter, when event > counters overflow, they would stop counting unless clear the counter, > and no interrupt generate for event counters. So we should clear event > counters that let them re-count when cycle counter overflow, which ensure > event counters will not lose data. Was this supposed to be an improvement over the "Legacy SoCs" implementation? It seems even worse... Do you _have_ to write zeroes back to the event counters to get them going again, or will any value do? > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c > index 90884d14f95f..057e361eb391 100644 > --- a/drivers/perf/fsl_imx8_ddr_perf.c > +++ b/drivers/perf/fsl_imx8_ddr_perf.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > > #define COUNTER_CNTL 0x0 > @@ -82,6 +83,7 @@ struct ddr_pmu { > const struct fsl_ddr_devtype_data *devtype_data; > int irq; > int id; > + spinlock_t lock; > }; > > enum ddr_perf_filter_capabilities { > @@ -368,16 +370,19 @@ static void ddr_perf_event_update(struct perf_event *event) > struct hw_perf_event *hwc = &event->hw; > u64 delta, prev_raw_count, new_raw_count; > int counter = hwc->idx; > + unsigned long flags; > > - do { > - prev_raw_count = local64_read(&hwc->prev_count); > - new_raw_count = ddr_perf_read_counter(pmu, counter); > - } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, > - new_raw_count) != prev_raw_count); > + spin_lock_irqsave(&pmu->lock, flags); > + > + prev_raw_count = local64_read(&hwc->prev_count); > + new_raw_count = ddr_perf_read_counter(pmu, counter); > > delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; > > local64_add(delta, &event->count); > + local64_set(&hwc->prev_count, new_raw_count); Hmm, assuming that the event counters never overflow, why do we care about the prev count at all? In other words, why don't we just add the counter value to event->count and reset the hardware to zero every time? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel