From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7FFFC433E2 for ; Tue, 8 Sep 2020 14:44:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 50488223E4 for ; Tue, 8 Sep 2020 14:44:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hXCXizmz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 50488223E4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eYFwB5NxAC7GbRj1CwjlfKMiNHcNot1V597rpPzZOqw=; b=hXCXizmzpIFq0Agwd4jv75a5j VeV4zIdO6EJ/sShgKznxaaEQSrj8wo9I/ZHpFb1Ym4yp+WbuMujZxXPX4gKrwcSXkl3+p8a6NM1t6 gUzKZIUNOtyNIkjeMTRhkdviPxFYnPROs8Bf7EY3klORWmy8aio/AV8OiCeRlxwoZeJZZaohUDege MKkSxrMryCTfPKydsYDUv/WosoIw6NQ0dBZ4p2y+FaiyRLe2MGdUPt5qtwm4eDT7TGAsDepoaaVS8 BuRid0lg5XXDcZiUHZwF01zXu4DORIl02DOKryegr1vcGiBVg7TnmZrGqq5h/w+Qe2J6yLCaeOzTt WTWuzsEKQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFeoe-00035U-VE; Tue, 08 Sep 2020 14:41:48 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFeod-00034w-9Q for linux-arm-kernel@lists.infradead.org; Tue, 08 Sep 2020 14:41:48 +0000 Received: from gaia (unknown [46.69.195.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E1F6221919; Tue, 8 Sep 2020 14:41:43 +0000 (UTC) Date: Tue, 8 Sep 2020 15:41:41 +0100 From: Catalin Marinas To: Andrey Konovalov Subject: Re: [PATCH 26/35] kasan, arm64: Enable TBI EL1 Message-ID: <20200908144140.GG25591@gaia> References: <518da1e5169a4e343caa3c37feed5ad551b77a34.1597425745.git.andreyknvl@google.com> <20200827104033.GF29264@gaia> <20200908140620.GE25591@gaia> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_104147_446597_48AD04F0 X-CRM114-Status: GOOD ( 28.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linux ARM , Marco Elver , Elena Petrova , Kevin Brodsky , Will Deacon , Branislav Rankov , kasan-dev , LKML , Linux Memory Management List , Alexander Potapenko , Evgenii Stepanov , Andrey Ryabinin , Andrew Morton , Vincenzo Frascino , Dmitry Vyukov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Sep 08, 2020 at 04:12:49PM +0200, Andrey Konovalov wrote: > On Tue, Sep 8, 2020 at 4:06 PM Catalin Marinas wrote: > > On Tue, Sep 08, 2020 at 03:18:04PM +0200, Andrey Konovalov wrote: > > > On Thu, Aug 27, 2020 at 12:40 PM Catalin Marinas > > > wrote: > > > > On Fri, Aug 14, 2020 at 07:27:08PM +0200, Andrey Konovalov wrote: > > > > > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > > > > > index 152d74f2cc9c..6880ddaa5144 100644 > > > > > --- a/arch/arm64/mm/proc.S > > > > > +++ b/arch/arm64/mm/proc.S > > > > > @@ -38,7 +38,7 @@ > > > > > /* PTWs cacheable, inner/outer WBWA */ > > > > > #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA > > > > > > > > > > -#ifdef CONFIG_KASAN_SW_TAGS > > > > > +#if defined(CONFIG_KASAN_SW_TAGS) || defined(CONFIG_KASAN_HW_TAGS) > > > > > #define TCR_KASAN_FLAGS TCR_TBI1 > > > > > #else > > > > > #define TCR_KASAN_FLAGS 0 > > > > > > > > I prefer to turn TBI1 on only if MTE is present. So on top of the v8 > > > > user series, just do this in __cpu_setup. > > > > > > Started working on this, but realized that I don't understand what > > > exactly is suggested here. TCR_KASAN_FLAGS are used in __cpu_setup(), > > > so this already happens in __cpu_setup(). > > > > > > Do you mean that TBI1 should be enabled when CONFIG_ARM64_MTE is > > > enabled, but CONFIG_KASAN_HW_TAGS is disabled? > > > > What I meant is that we should turn TBI1 only when the MTE is present in > > hardware (and the ARM64_MTE option is on). But I probably missed the way > > MTE is used with KASAN. > > > > So what happens if CONFIG_KASAN_HW_TAGS and CONFIG_ARM64_MTE are both on > > but the hardware does not support MTE? Does KASAN still generate tagged > > pointers? If yes, then the current patch is fine, we should always set > > TBI1. > > No, the tag is always 0xFF when MTE is not supported. > > Should we then only enable TBI1 if system_supports_mte() or something > like that? You could add it do this block in __cpu_setup: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/tree/arch/arm64/mm/proc.S?h=for-next/mte#n429 It needs a few changes to have "mov_q x10, TCR_..." before the MTE check so that you can add the TBI1 bit in there. system_supports_mte() would be called too late, you want this set before the MMU is turned on. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel