From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Jonathan Zhou <jonathan.zhouwen@huawei.com>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>,
lizixian@hisilicon.com, Mike Leach <mike.leach@linaro.org>,
linux-arm-kernel@lists.infradead.org,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: Re: [PATCH] coresight: etm4x: fix issues on trcseqevr access
Date: Wed, 9 Sep 2020 10:42:46 -0600 [thread overview]
Message-ID: <20200909164246.GD553266@xps15> (raw)
In-Reply-To: <1599043033-57852-1-git-send-email-jonathan.zhouwen@huawei.com>
On Wed, Sep 02, 2020 at 06:37:13PM +0800, Jonathan Zhou wrote:
> The TRCSEQEVR(3) is reserved, using '@nrseqstate - 1' instead to avoid
> accessing the reserved register.
>
> Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
> Cc: lizixian@hisilicon.com
>
> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
I have applied this patch.
Thanks,
Mathieu
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 96425e818fc2..44e44c817bf8 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -1183,7 +1183,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
> state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
>
> - for (i = 0; i < drvdata->nrseqstate; i++)
> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i));
>
> state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR);
> @@ -1288,7 +1288,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
> writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
>
> - for (i = 0; i < drvdata->nrseqstate; i++)
> + for (i = 0; i < drvdata->nrseqstate - 1; i++)
> writel_relaxed(state->trcseqevr[i],
> drvdata->base + TRCSEQEVRn(i));
>
> --
> 1.9.1
>
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prev parent reply other threads:[~2020-09-09 16:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-02 10:37 [PATCH] coresight: etm4x: fix issues on trcseqevr access Jonathan Zhou
2020-09-03 17:42 ` Mathieu Poirier
2020-09-07 16:51 ` Mike Leach
2020-09-08 1:39 ` Jonathan Zhou
2020-09-08 17:43 ` Mathieu Poirier
2020-09-09 9:41 ` Mike Leach
2020-09-09 16:32 ` Mathieu Poirier
2020-09-09 16:42 ` Mathieu Poirier [this message]
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