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From: Catalin Marinas <catalin.marinas@arm.com>
To: Steven Price <steven.price@arm.com>
Cc: linux-arch@vger.kernel.org, Szabolcs Nagy <szabolcs.nagy@arm.com>,
	Andrey Konovalov <andreyknvl@google.com>,
	Kevin Brodsky <kevin.brodsky@arm.com>,
	Peter Collingbourne <pcc@google.com>,
	linux-mm@kvack.org, Andrew Morton <akpm@linux-foundation.org>,
	Vincenzo Frascino <vincenzo.frascino@arm.com>,
	Will Deacon <will@kernel.org>,
	Dave P Martin <Dave.Martin@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v9 09/29] arm64: mte: Clear the tags when a page is mapped in user-space with PROT_MTE
Date: Thu, 10 Sep 2020 11:52:58 +0100	[thread overview]
Message-ID: <20200910105258.GA4030@gaia> (raw)
In-Reply-To: <5c2ebe16-2ac9-6cff-3456-6d8ac96b5fb7@arm.com>

On Thu, Sep 10, 2020 at 11:23:33AM +0100, Steven Price wrote:
> On 04/09/2020 11:30, Catalin Marinas wrote:
> > --- /dev/null
> > +++ b/arch/arm64/lib/mte.S
> > @@ -0,0 +1,34 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2020 ARM Ltd.
> > + */
> > +#include <linux/linkage.h>
> > +
> > +#include <asm/assembler.h>
> > +#include <asm/sysreg.h>
> > +
> > +	.arch	armv8.5-a+memtag
> > +
> > +/*
> > + * multitag_transfer_size - set \reg to the block size that is accessed by the
> > + * LDGM/STGM instructions.
> > + */
> > +	.macro	multitag_transfer_size, reg, tmp
> > +	mrs_s	\reg, SYS_GMID_EL1
> > +	ubfx	\reg, \reg, #SYS_GMID_EL1_BS_SHIFT, #SYS_GMID_EL1_BS_SIZE
> > +	mov	\tmp, #4
> > +	lsl	\reg, \tmp, \reg
> > +	.endm
> > +
> > +/*
> > + * Clear the tags in a page
> > + *   x0 - address of the page to be cleared
> > + */
> > +SYM_FUNC_START(mte_clear_page_tags)
> > +	multitag_transfer_size x1, x2
> > +1:	stgm	xzr, [x0]
> > +	add	x0, x0, x1
> > +	tst	x0, #(PAGE_SIZE - 1)
> > +	b.ne	1b
> > +	ret
> > +SYM_FUNC_END(mte_clear_page_tags)
> 
> Could the value of SYS_GMID_EL1 vary between CPUs and do we therefore need a
> preempt_disable() around mte_clear_page_tags() (and other functions in later
> patches)?

If they differ, disabling preemption here is not sufficient. We'd have
to trap the GMID_EL1 access at EL2 as well and emulate it (we do this
for CTR_EL0 in dcache_line_size).

I don't want to proactively implement this just in case we'll have
broken hardware (I feel a bit more optimistic today ;)).

-- 
Catalin

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  reply	other threads:[~2020-09-10 10:54 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20200904103029.32083-1-catalin.marinas@arm.com>
     [not found] ` <20200904103029.32083-5-catalin.marinas@arm.com>
2020-09-04 10:46   ` [PATCH v9 04/29] arm64: kvm: mte: Hide the MTE CPUID information from the guests Marc Zyngier
     [not found] ` <20200904103029.32083-10-catalin.marinas@arm.com>
2020-09-10 10:23   ` [PATCH v9 09/29] arm64: mte: Clear the tags when a page is mapped in user-space with PROT_MTE Steven Price
2020-09-10 10:52     ` Catalin Marinas [this message]
2020-09-10 11:12       ` Steven Price
2020-09-10 11:55         ` Catalin Marinas
2020-09-10 12:43           ` Steven Price
     [not found] ` <20200904103029.32083-30-catalin.marinas@arm.com>
2020-09-17  8:11   ` [PATCH v9 29/29] arm64: mte: Add Memory Tagging Extension documentation Will Deacon
2020-09-17  9:02     ` Catalin Marinas
2020-09-17 16:15       ` Dave Martin
2020-09-18  8:30         ` Will Deacon
2020-10-14 23:43           ` Peter Collingbourne
2020-10-15  8:57             ` Will Deacon
2020-10-15 11:14             ` Szabolcs Nagy
2020-09-22 16:04         ` Catalin Marinas
2020-09-22 15:52       ` Szabolcs Nagy
2020-09-22 16:55         ` Catalin Marinas
2020-09-23  9:10           ` Szabolcs Nagy
2020-09-22 12:22   ` Andrey Konovalov

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