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10 Sep 2020 16:42:59 +0000 Received: from EX13MTAUWC002.ant.amazon.com (iad12-ws-svc-p26-lb9-vlan2.iad.amazon.com [10.40.163.34]) by email-inbound-relay-1d-38ae4ad2.us-east-1.amazon.com (Postfix) with ESMTPS id 80B89A240F; Thu, 10 Sep 2020 16:42:56 +0000 (UTC) Received: from EX13D20UWC001.ant.amazon.com (10.43.162.244) by EX13MTAUWC002.ant.amazon.com (10.43.162.240) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Sep 2020 16:42:53 +0000 Received: from u79c5a0a55de558.ant.amazon.com (10.43.161.85) by EX13D20UWC001.ant.amazon.com (10.43.162.244) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Sep 2020 16:42:51 +0000 From: Alexander Graf To: Subject: [PATCH v3] KVM: arm64: Preserve PMCR immutable values across reset Date: Thu, 10 Sep 2020 18:42:43 +0200 Message-ID: <20200910164243.29253-1-graf@amazon.com> X-Mailer: git-send-email 2.28.0.394.ge197136389 MIME-Version: 1.0 X-Originating-IP: [10.43.161.85] X-ClientProxiedBy: EX13D40UWA004.ant.amazon.com (10.43.160.36) To EX13D20UWC001.ant.amazon.com (10.43.162.244) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200910_124551_167327_CCDF061A X-CRM114-Status: GOOD ( 16.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Andrew Jones , kvm@vger.kernel.org, Suzuki K Poulose , Marc Zyngier , Eric Auger , James Morse , linux-arm-kernel@lists.infradead.org, Robin Murphy , Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We allow user space to set the PMCR register to any value. However, when time comes for a vcpu reset (for example on PSCI online), PMCR is reset to the hardware capabilities. I would like to explicitly expose different PMU capabilities (number of supported event counters) to the guest than hardware supports. Ideally across vcpu resets. So this patch adopts the reset path to only populate the immutable PMCR register bits from hardware when they were not initialized previously. This effectively means that on a normal reset, only the guest settable fields are reset, while on vcpu creation the register gets populated from hardware like before. With this in place and a change in user space to invoke SET_ONE_REG on the PMCR for every vcpu, I can reliably set the PMU event counter number to arbitrary values. Signed-off-by: Alexander Graf --- arch/arm64/kvm/sys_regs.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 20ab2a7d37ca..28f67550db7f 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -663,7 +663,14 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { u64 pmcr, val; - pmcr = read_sysreg(pmcr_el0); + /* + * If we already received PMCR from a previous ONE_REG call, + * maintain its immutable flags + */ + pmcr = __vcpu_sys_reg(vcpu, r->reg); + if (!__vcpu_sys_reg(vcpu, r->reg)) + pmcr = read_sysreg(pmcr_el0); + /* * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN * except PMCR.E resetting to zero. -- 2.16.4 Amazon Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B Sitz: Berlin Ust-ID: DE 289 237 879 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel