From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A591C433E2 for ; Fri, 11 Sep 2020 10:38:32 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1DB342076D for ; Fri, 11 Sep 2020 10:38:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ntsLfqZU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1DB342076D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=jzdJwtKHebP8x9ckPPanU5bKLWex8Z/D9sUtjIPVnN4=; b=ntsLfqZUj+WZ+Jvl6tZ+SIEil M87tG10HNQbY0YPW0FdlgT1dI4vQT5HBsrVnfmPcwgL3K4/H3vWmZWrEcJwTshy+8x9m2O/1GHYCi AHvwDfcJPU5kn/UknjRmCBqgkwh4grwzPkD9lL3BcDOX/DaKxNlTJgwCtjr60RvnA9G8fwOA4hOh6 zw5F+/M62W4qD1OjtDRyQ58TxOUGNBn37nl4CC4eWUaArpQiWmWRzsHKMr47JdT5hGISJLWSuaSeY 4pGJK2dIp+IOIvFQi32z/RHn+d3+Sw8pPw+hCdXEk5GbMZ6hYbCxDI8yC7gPPhjmnehtptIisuwIj 0erSL5klw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kGgQk-00066K-El; Fri, 11 Sep 2020 10:37:22 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kGgQh-00064w-QS for linux-arm-kernel@lists.infradead.org; Fri, 11 Sep 2020 10:37:20 +0000 Received: from gaia (unknown [46.69.195.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 29C36208FE; Fri, 11 Sep 2020 10:37:17 +0000 (UTC) Date: Fri, 11 Sep 2020 11:37:14 +0100 From: Catalin Marinas To: Rob Herring Subject: Re: [PATCH v5 2/2] arm64: Add workaround for Arm Cortex-A77 erratum 1508412 Message-ID: <20200911103714.GA4094@gaia> References: <20200909231310.3297400-1-robh@kernel.org> <20200909231310.3297400-2-robh@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200909231310.3297400-2-robh@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_063719_931234_7989ABDC X-CRM114-Status: GOOD ( 16.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , Marc Zyngier , James Morse , linux-arm-kernel@lists.infradead.org, Will Deacon , kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 09, 2020 at 05:13:10PM -0600, Rob Herring wrote: > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 554a7e8ecb07..55dfff8ca466 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -943,6 +943,7 @@ > > #include > #include > +#include > > #define __DEFINE_MRS_MSR_S_REGNUM \ > " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ > @@ -1024,6 +1025,17 @@ > write_sysreg(__scs_new, sysreg); \ > } while (0) > > +#define read_sysreg_par() ({ \ > + unsigned long flags; \ > + u64 par; \ > + local_irq_save(flags); \ > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ > + par = read_sysreg(par_el1); \ > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ > + local_irq_restore(flags); \ > + par; \ > +}) As an alternative to local_irq_save/restore, we could have added a dmb in the kernel_exit macro. The minor nit here is that we always disable interrupts even when the erratum doesn't apply. The EL1 code accessing PAR_EL1 already runs with interrupts disabled (which covers the prior AT instruction). If that's the case for KVM as well, we could drop the local_irq_* entirely and just leave the DMB in the exit to guest code. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel