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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kGlBO-0008R7-Nn; Fri, 11 Sep 2020 15:41:50 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kGlBM-0008Qe-1y for linux-arm-kernel@lists.infradead.org; Fri, 11 Sep 2020 15:41:48 +0000 Received: from gaia (unknown [46.69.195.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A9C6C20758; Fri, 11 Sep 2020 15:41:45 +0000 (UTC) Date: Fri, 11 Sep 2020 16:41:43 +0100 From: Catalin Marinas To: Will Deacon Subject: Re: [PATCH v5 2/2] arm64: Add workaround for Arm Cortex-A77 erratum 1508412 Message-ID: <20200911154142.GK12835@gaia> References: <20200909231310.3297400-1-robh@kernel.org> <20200909231310.3297400-2-robh@kernel.org> <20200911103714.GA4094@gaia> <20200911152807.GA20527@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200911152807.GA20527@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_114148_172205_BE523C10 X-CRM114-Status: GOOD ( 22.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Suzuki K Poulose , Marc Zyngier , James Morse , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 11, 2020 at 04:28:07PM +0100, Will Deacon wrote: > On Fri, Sep 11, 2020 at 11:37:14AM +0100, Catalin Marinas wrote: > > On Wed, Sep 09, 2020 at 05:13:10PM -0600, Rob Herring wrote: > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > > index 554a7e8ecb07..55dfff8ca466 100644 > > > --- a/arch/arm64/include/asm/sysreg.h > > > +++ b/arch/arm64/include/asm/sysreg.h > > > @@ -943,6 +943,7 @@ > > > > > > #include > > > #include > > > +#include > > > > > > #define __DEFINE_MRS_MSR_S_REGNUM \ > > > " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ > > > @@ -1024,6 +1025,17 @@ > > > write_sysreg(__scs_new, sysreg); \ > > > } while (0) > > > > > > +#define read_sysreg_par() ({ \ > > > + unsigned long flags; \ > > > + u64 par; \ > > > + local_irq_save(flags); \ > > > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ > > > + par = read_sysreg(par_el1); \ > > > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ > > > + local_irq_restore(flags); \ > > > + par; \ > > > +}) > > > > As an alternative to local_irq_save/restore, we could have added a dmb > > in the kernel_exit macro. The minor nit here is that we always disable > > interrupts even when the erratum doesn't apply. > > > > The EL1 code accessing PAR_EL1 already runs with interrupts disabled > > (which covers the prior AT instruction). If that's the case for KVM as > > well, we could drop the local_irq_* entirely and just leave the DMB in > > the exit to guest code. > > I wonder if that's actually a more robust approach in the case of psuedo > NMIs using ARM64_HAS_IRQ_PRIO_MASKING? Good point, so better do the dmb on the return path for both kernel and hyp. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel