From: Catalin Marinas <catalin.marinas@arm.com>
To: Amit Daniel Kachhap <amit.kachhap@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mark Brown <broonie@kernel.org>,
James Morse <james.morse@arm.com>,
Vincenzo Frascino <Vincenzo.Frascino@arm.com>,
Will Deacon <will@kernel.org>, Dave Martin <Dave.Martin@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v8 4/6] arm64: cpufeature: Modify address authentication cpufeature to exact
Date: Mon, 14 Sep 2020 11:22:25 +0100 [thread overview]
Message-ID: <20200914102224.GB32700@gaia> (raw)
In-Reply-To: <20200914083656.21428-5-amit.kachhap@arm.com>
On Mon, Sep 14, 2020 at 02:06:54PM +0530, Amit Daniel Kachhap wrote:
> The current address authentication cpufeature levels are set as LOWER_SAFE
> which is not compatible with the different configurations added for Armv8.3
> ptrauth enhancements as the different levels have different behaviour and
> there is no tunable to enable the lower safe versions. This is rectified
> by setting those cpufeature type as EXACT.
>
> The current cpufeature framework also does not interfere in the booting of
> non-exact secondary cpus but rather marks them as tainted. As a workaround
> this is fixed by replacing the generic match handler with a new handler
> specific to ptrauth.
>
> After this change, if there is any variation in ptrauth configurations in
> secondary cpus from boot cpu then those mismatched cpus are parked in an
> infinite loop.
>
> Following ptrauth crash log is observed in Arm fastmodel with simulated
> mismatched cpus without this fix,
>
> CPU features: SANITY CHECK: Unexpected variation in SYS_ID_AA64ISAR1_EL1. Boot CPU: 0x11111110211402, CPU4: 0x11111110211102
> CPU features: Unsupported CPU feature variation detected.
> GICv3: CPU4: found redistributor 100 region 0:0x000000002f180000
> CPU4: Booted secondary processor 0x0000000100 [0x410fd0f0]
> Unable to handle kernel paging request at virtual address bfff800010dadf3c
> Mem abort info:
> ESR = 0x86000004
> EC = 0x21: IABT (current EL), IL = 32 bits
> SET = 0, FnV = 0
> EA = 0, S1PTW = 0
> [bfff800010dadf3c] address between user and kernel address ranges
> Internal error: Oops: 86000004 [#1] PREEMPT SMP
> Modules linked in:
> CPU: 4 PID: 29 Comm: migration/4 Tainted: G S 5.8.0-rc4-00005-ge658591d66d1-dirty #158
> Hardware name: Foundation-v8A (DT)
> pstate: 60000089 (nZCv daIf -PAN -UAO BTYPE=--)
> pc : 0xbfff800010dadf3c
> lr : __schedule+0x2b4/0x5a8
> sp : ffff800012043d70
> x29: ffff800012043d70 x28: 0080000000000000
> x27: ffff800011cbe000 x26: ffff00087ad37580
> x25: ffff00087ad37000 x24: ffff800010de7d50
> x23: ffff800011674018 x22: 0784800010dae2a8
> x21: ffff00087ad37000 x20: ffff00087acb8000
> x19: ffff00087f742100 x18: 0000000000000030
> x17: 0000000000000000 x16: 0000000000000000
> x15: ffff800011ac1000 x14: 00000000000001bd
> x13: 0000000000000000 x12: 0000000000000000
> x11: 0000000000000000 x10: 71519a147ddfeb82
> x9 : 825d5ec0fb246314 x8 : ffff00087ad37dd8
> x7 : 0000000000000000 x6 : 00000000fffedb0e
> x5 : 00000000ffffffff x4 : 0000000000000000
> x3 : 0000000000000028 x2 : ffff80086e11e000
> x1 : ffff00087ad37000 x0 : ffff00087acdc600
> Call trace:
> 0xbfff800010dadf3c
> schedule+0x78/0x110
> schedule_preempt_disabled+0x24/0x40
> __kthread_parkme+0x68/0xd0
> kthread+0x138/0x160
> ret_from_fork+0x10/0x34
> Code: bad PC value
>
> After this fix, the mismatched CPU4 is parked as,
> CPU features: CPU4: Detected conflict for capability 39 (Address authentication (IMP DEF algorithm)), System: 1, CPU: 0
> CPU4: will not boot
> CPU4: failed to come online
> CPU4: died during early boot
>
> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
> [Suzuki: Introduce new matching function for address authentication]
> Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
It looks fine to me.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-14 10:23 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-14 8:36 [PATCH v8 0/6] arm64: add Armv8.3 pointer authentication enhancements Amit Daniel Kachhap
2020-09-14 8:36 ` [PATCH v8 1/6] arm64: kprobe: add checks for ARMv8.3-PAuth combined instructions Amit Daniel Kachhap
2020-09-14 8:36 ` [PATCH v8 2/6] arm64: traps: Allow force_signal_inject to pass esr error code Amit Daniel Kachhap
2020-09-14 8:36 ` [PATCH v8 3/6] arm64: ptrauth: Introduce Armv8.3 pointer authentication enhancements Amit Daniel Kachhap
2020-09-14 8:36 ` [PATCH v8 4/6] arm64: cpufeature: Modify address authentication cpufeature to exact Amit Daniel Kachhap
2020-09-14 10:22 ` Catalin Marinas [this message]
2020-09-14 8:36 ` [PATCH v8 5/6] arm64: kprobe: disable probe of fault prone ptrauth instruction Amit Daniel Kachhap
2020-09-14 8:36 ` [PATCH v8 6/6] arm64: kprobe: clarify the comment of steppable hint instructions Amit Daniel Kachhap
2020-09-14 12:16 ` [PATCH v8 0/6] arm64: add Armv8.3 pointer authentication enhancements Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200914102224.GB32700@gaia \
--to=catalin.marinas@arm.com \
--cc=Dave.Martin@arm.com \
--cc=Vincenzo.Frascino@arm.com \
--cc=amit.kachhap@arm.com \
--cc=broonie@kernel.org \
--cc=james.morse@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=suzuki.poulose@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox