Re: [PATCH v3 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines

Peter Rosin
2020-09-16T04:54:53Z

Hi,

Sorry for the delay.

On 2020-09-15 13:20, Roger Quadros wrote:
> Each SERDES lane mux can select upto 4 different IPs.
> There are 4 lanes in each J7200 SERDES. Define all
> the possible functions in this file.
>
> Cc: Peter Rosin <peda@axentia.se>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> include/dt-bindings/mux/mux-j7200-wiz.h | 29 +++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 include/dt-bindings/mux/mux-j7200-wiz.h
>
> diff --git a/include/dt-bindings/mux/mux-j7200-wiz.h b/include/dt-bindings/mux/mux-j7200-wiz.h
> new file mode 100644
> index 000000000000..b091b1185a36
> --- /dev/null
> +++ b/include/dt-bindings/mux/mux-j7200-wiz.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for J7200 WIZ.
> + */
> +
> +#ifndef _DT_BINDINGS_J7200_WIZ
> +#define _DT_BINDINGS_J7200_WIZ
> +
> +#define SERDES0_LANE0_QSGMII_LANE3 0x0
> +#define SERDES0_LANE0_PCIE1_LANE0 0x1
> +#define SERDES0_LANE0_IP3_UNUSED 0x2
> +#define SERDES0_LANE0_IP4_UNUSED 0x3
> +
> +#define SERDES0_LANE1_QSGMII_LANE4 0x0
> +#define SERDES0_LANE1_PCIE1_LANE1 0x1
> +#define SERDES0_LANE1_IP3_UNUSED 0x2
> +#define SERDES0_LANE1_IP4_UNUSED 0x3
> +
> +#define SERDES0_LANE2_QSGMII_LANE1 0x0
> +#define SERDES0_LANE2_PCIE1_LANE2 0x1
> +#define SERDES0_LANE2_IP3_UNUSED 0x2
> +#define SERDES0_LANE2_IP4_UNUSED 0x3
> +
> +#define SERDES0_LANE3_QSGMII_LANE2 0x0
> +#define SERDES0_LANE3_PCIE1_LANE3 0x1
> +#define SERDES0_LANE3_USB 0x2
> +#define SERDES0_LANE3_IP4_UNUSED 0x3
> +
> +#endif /* _DT_BINDINGS_J7200_WIZ */

Should not the defines start with J7200_WIZ? SERDES0 seems like a too
generic prefix, at least to me.

Cheers,
Peter