From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 057B0C43469 for ; Mon, 21 Sep 2020 13:46:20 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2A93207C3 for ; Mon, 21 Sep 2020 13:46:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="sEwKbf2x"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="glGVInNp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2A93207C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ONpY6VaMWsNikYCeeSdg9ITVbYT6tuiKPLgesWMQHr4=; b=sEwKbf2xkbe9s22XxxpJFPd8v z54hFL7fCqg3GgjFomiuKJlFsthafhZGt+SDG+NBeYBpExUirxXBIslyr6ukImcw/9MPZMHdXTbrW 24ouz5LB75g2061f0jJ8gx5bXI8DkfnhqyY/zo0Q/X9RCtGgB4yZuV7CTP+kzgJ3iRGjk9ZqGc3r5 wNHYnDXJd3LtcGuMezoFftIigxF3BN/bUZVr47z/EIKcrjxCA5qcH8lj7x0dLr2yHHa34lEpfGuTh 7b6d5qCbVJVxV/KGvIScBL1I1/dvFMGJuPQ4UgKKIWq3XYuW4exCuYRkfooCVukiXtWrCFG8V568/ AtTns0L3g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKM7i-00035z-LM; Mon, 21 Sep 2020 13:44:54 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKM6v-0002o5-Md for linux-arm-kernel@lists.infradead.org; Mon, 21 Sep 2020 13:44:07 +0000 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B269220888; Mon, 21 Sep 2020 13:44:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600695844; bh=MWMbTeQXgsSrcke9ClQCdlLOJJmrD/yGsUoAPqwbB1c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=glGVInNpxoukIMGGUaJ7ob5aWbbmyaI3ZQ0mPg5DXA71utsj8OfFA/4d6AD47Gn3h ee1v1lAsMEkPgVJWp0qDUrlMre9NV6ogj4CXNgd+OVS7lNP+AnmAXrmlOg8xlOo6sM FLIUhvOeKaR2/dW/EY0bbeqkzOOHXbaDFSykNsoM= Date: Mon, 21 Sep 2020 14:43:58 +0100 From: Will Deacon To: Alexandru Elisei Subject: Re: [PATCH v6 2/7] arm64: perf: Avoid PMXEV* indirection Message-ID: <20200921134357.GL2139@willie-the-truck> References: <20200819133419.526889-1-alexandru.elisei@arm.com> <20200819133419.526889-3-alexandru.elisei@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200819133419.526889-3-alexandru.elisei@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200921_094405_911025_54219B66 X-CRM114-Status: GOOD ( 26.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, sumit.garg@linaro.org, Julien Thierry , Peter Zijlstra , maz@kernel.org, Will Deacon , linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , swboyd@chromium.org, Alexander Shishkin , Ingo Molnar , Julien Thierry , catalin.marinas@arm.com, Namhyung Kim , Jiri Olsa , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 19, 2020 at 02:34:14PM +0100, Alexandru Elisei wrote: > From: Mark Rutland > > Currently we access the counter registers and their respective type > registers indirectly. This requires us to write to PMSELR, issue an ISB, > then access the relevant PMXEV* registers. > > This is unfortunate, because: > > * Under virtualization, accessing one register requires two traps to > the hypervisor, even though we could access the register directly with > a single trap. > > * We have to issue an ISB which we could otherwise avoid the cost of. > > * When we use NMIs, the NMI handler will have to save/restore the select > register in case the code it preempted was attempting to access a > counter or its type register. > > We can avoid these issues by directly accessing the relevant registers. > This patch adds helpers to do so. > > In armv8pmu_enable_event() we still need the ISB to prevent the PE from > reordering the write to PMINTENSET_EL1 register. If the interrupt is > enabled before we disable the counter and the new event is configured, > we might get an interrupt triggered by the previously programmed event > overflowing, but which we wrongly attribute to the event that we are > enabling. > > In the process, remove the comment that refers to the ARMv7 PMU. > > Cc: Julien Thierry > Cc: Will Deacon > Cc: Peter Zijlstra > Cc: Ingo Molnar > Cc: Arnaldo Carvalho de Melo > Cc: Alexander Shishkin > Cc: Jiri Olsa > Cc: Namhyung Kim > Cc: Catalin Marinas > Signed-off-by: Mark Rutland > [Julien T.: Don't inline read/write functions to avoid big code-size > increase, remove unused read_pmevtypern function, > fix counter index issue.] > Signed-off-by: Julien Thierry > [Removed comment, removed trailing semicolons in macros, added ISB] nit: but it's customary to prefix these with your name, so it's easy to figure out who made changes (like Julien did above). (similar comment for other patches in this series) > @@ -620,9 +686,14 @@ static void armv8pmu_enable_event(struct perf_event *event) > * Disable counter > */ > armv8pmu_disable_event_counter(event); > + /* > + * Make sure the effects of disabling the counter are visible before we > + * start configuring the event. > + */ > + isb(); With the isb() added by patch 1, why don't we just make these implicit in armv8_{enable,disable}_event_counter() ? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel