From: Maxime Ripard <maxime@cerno.tech>
To: Dave Stevenson <dave.stevenson@raspberrypi.com>
Cc: Tim Gover <tim.gover@raspberrypi.com>,
DRI Development <dri-devel@lists.freedesktop.org>,
Hoegeun Kwon <hoegeun.kwon@samsung.com>,
Eric Anholt <eric@anholt.net>,
bcm-kernel-feedback-list@broadcom.com,
linux-rpi-kernel@lists.infradead.org,
Phil Elwell <phil@raspberrypi.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] drm/vc4: hvs: Pull the state of all the CRTCs prior to PV muxing
Date: Mon, 21 Sep 2020 16:43:52 +0200 [thread overview]
Message-ID: <20200921144352.deohjbuzlo4xq2gx@gilmour.lan> (raw)
In-Reply-To: <CAPY8ntDG9fDZ6WwreTCMk_2GedqtDAvQuRD6iiM_YUeEbtS9+Q@mail.gmail.com>
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On Fri, Sep 18, 2020 at 03:52:55PM +0100, Dave Stevenson wrote:
> Hi Maxime
>
> On Thu, 17 Sep 2020 at 13:16, Maxime Ripard <maxime@cerno.tech> wrote:
> >
> > The vc4 display engine has a first controller called the HVS that will
> > perform the composition of the planes. That HVS has 3 FIFOs and can
> > therefore compose planes for up to three outputs. The timings part is
> > generated through a component called the Pixel Valve, and the BCM2711 has 6
> > of them.
> >
> > Thus, the HVS has some bits to control which FIFO gets output to which
> > Pixel Valve. The current code supports that muxing by looking at all the
> > CRTCs in a new DRM atomic state in atomic_check, and given the set of
> > contraints that we have, assigns FIFOs to CRTCs or reject the mode
>
> s/contraints/constraints
Oops, thanks
I've fixed it while applying it
Maxime
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prev parent reply other threads:[~2020-09-21 14:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20200917140744epcas1p4ae14fb989c92453b3b3d0defc171446d@epcas1p4.samsung.com>
2020-09-17 12:16 ` [PATCH] drm/vc4: hvs: Pull the state of all the CRTCs prior to PV muxing Maxime Ripard
2020-09-18 6:53 ` Hoegeun Kwon
2020-09-18 14:52 ` Dave Stevenson
2020-09-21 14:43 ` Maxime Ripard [this message]
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