From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18162C4363C for ; Mon, 21 Sep 2020 21:12:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A96C823A5C for ; Mon, 21 Sep 2020 21:12:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="vMLx5yc3"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="vWqcFEnU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A96C823A5C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TSJUQzCeIVJxZRQJXo+uDEaehVh05NqZ/dHKTCS7kCY=; b=vMLx5yc3UQ8TDr7RGXv16gaoA d5eYkdWjNCOpJjmR0ahsivecrlzl8MknO9W7HdDczTDiHFaHwaqOKAR8Q+4QrWB6UYYYjhrtasK2M W8UGHicXlGfK6OIvEOaNNRNBEORlGkBzFGpII8jVgI8Z1ZWkpz67Ziu5upo9TlbMlsQ7JQf63E5wJ JpNa4IIy37yESlCoIlLCFH3+DSukZ+exkukJIGI95R0bVi6sEc5DxHwsF/ZDpRPNP1CSajT8EILdo bMcz9WQwNnb23xp7ilt3/AV6IIF7lLN65hMoLNtiUdEzSSNqepjUN5R5rQfd/wCCk+4w3mil7uxLG zaL2dLy7w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKT54-0007GX-Ak; Mon, 21 Sep 2020 21:10:39 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKSwk-0002qn-GU for linux-arm-kernel@lists.infradead.org; Mon, 21 Sep 2020 21:02:05 +0000 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B42F0207BC; Mon, 21 Sep 2020 21:01:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600722120; bh=oSItkIQL1MkIiICl93p1wBrpqBIgnKcstXciRYG8N8M=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=vWqcFEnUhzS1Z4/hlYVk2+jvA7m3DwVhkIh9rf26NBrfYxDpVwlKz1FsJwFww6hxc r/uN7hsLVKzCQ0wtI+H3Q1IB9soc9gEXWdtlgNz9gkNUaC78Y8fFYfQWQnnZVxJqGw 23101tC9miEObvCAEHT5gkSV1R4xrkt2kGW8Sdto= Date: Mon, 21 Sep 2020 22:01:56 +0100 From: Will Deacon To: Shaokun Zhang Subject: Re: [PATCH v7] arm64: perf: Add support caps in sysfs Message-ID: <20200921210156.GD3811@willie-the-truck> References: <1599898042-10635-1-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1599898042-10635-1-git-send-email-zhangshaokun@hisilicon.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200921_170203_046679_822CB0E5 X-CRM114-Status: GOOD ( 24.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Sep 12, 2020 at 04:07:22PM +0800, Shaokun Zhang wrote: > ARMv8.4-PMU introduces the PMMIR_EL1 registers and some new PMU events, > like STALL_SLOT etc, are related to it. Let's add a caps directory to > /sys/bus/event_source/devices/armv8_pmuv3_0/ and support slots from > PMMIR_EL1 registers in this entry. The user programs can get the slots > from sysfs directly. > > /sys/bus/event_source/devices/armv8_pmuv3_0/caps/slots is exposed > through sysfs. Both ARMv8.4-PMU and STALL_SLOT event are implemented, > it returns the slots from PMMIR_EL1, otherwise it will return 0. > > Cc: Will Deacon > Cc: Mark Rutland > Signed-off-by: Shaokun Zhang > --- > ChangeLog in v7: > * If this feature is not supported, return 0. [...] > arch/arm64/include/asm/perf_event.h | 3 ++ > arch/arm64/include/asm/sysreg.h | 2 + > arch/arm64/kernel/perf_event.c | 103 ++++++++++++++++++++++++------------ > include/linux/perf/arm_pmu.h | 3 ++ > 4 files changed, 78 insertions(+), 33 deletions(-) > > diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h > index 2c2d7dbe8a02..60731f602d3e 100644 > --- a/arch/arm64/include/asm/perf_event.h > +++ b/arch/arm64/include/asm/perf_event.h > @@ -236,6 +236,9 @@ > #define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */ > #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ > > +/* PMMIR_EL1.SLOTS mask */ > +#define ARMV8_PMU_SLOTS_MASK 0xff > + > #ifdef CONFIG_PERF_EVENTS > struct pt_regs; > extern unsigned long perf_instruction_pointer(struct pt_regs *regs); > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 554a7e8ecb07..921773adff5e 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -321,6 +321,8 @@ > #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) > #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) > > +#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) > + > #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) > #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > index 462f9a9cc44b..953d92145908 100644 > --- a/arch/arm64/kernel/perf_event.c > +++ b/arch/arm64/kernel/perf_event.c > @@ -302,6 +302,28 @@ static struct attribute_group armv8_pmuv3_format_attr_group = { > .attrs = armv8_pmuv3_format_attrs, > }; > > +static ssize_t slots_show(struct device *dev, struct device_attribute *attr, > + char *page) > +{ > + struct pmu *pmu = dev_get_drvdata(dev); > + struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); > + int slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK; > + > + return snprintf(page, PAGE_SIZE, "0x%02x\n", slots); I'm a little bit nervous about %02x here, as future versions of the architecture could extend PMMIR.SLOTS and parsers would have a bit of a rotten time dealing with the new immediates. Why don't we just make it %08x instead, and have 'int slots' be 'u32 slots'? Otherwise patch looks fine, thanks. Happy to apply a new version with that change. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel