From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DFE2C2D0E2 for ; Tue, 22 Sep 2020 10:15:01 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DE321238D6 for ; Tue, 22 Sep 2020 10:15:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="vxdGBYBW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DE321238D6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xxmRUhXLzw1pRcGcFzHQ1DIllI92a4B/Iu8/ByhOkGE=; b=vxdGBYBW7XGqgxWI61o/1Ys58k r7PidGsOxSp/7uIVGEFpjrlTL1IBo6cv+9ndwIJhxVfWlCHYfgOQjhsfLunWTM+Eo8gxEkwFrFbuy 0Hdu5KfIn8lSlR4tqcqfILrDSA/mAqen0t8AYJbhWsuMGK/OHkOxXkA19yA5dZuR9WEpFTYmdjfIj Ch5zGXQOxzuS5ZkqZJTpAwjKWTla2p1HfyyxcLw1v2+pV/6umpVDmK5HSzSfncT2PgaULzdRouWNT MTp+qFT+0Dmew6B8xWsiY4myXMuKbW1Inb4mY6aXGBYYbWbICIx9tjaLUXsdVTOIdGQgAF3/C2PuU e8ieRnzA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfIW-0006dL-1v; Tue, 22 Sep 2020 10:13:20 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKfHw-0006Vb-A5 for linux-arm-kernel@lists.infradead.org; Tue, 22 Sep 2020 10:12:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EDD1613D5; Tue, 22 Sep 2020 03:12:42 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.195.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F03373F718; Tue, 22 Sep 2020 03:12:40 -0700 (PDT) From: Andre Przywara To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo Subject: [PATCH 5/5] perf: arm_spe: Decode SVE events Date: Tue, 22 Sep 2020 11:12:25 +0100 Message-Id: <20200922101225.183554-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200922101225.183554-1-andre.przywara@arm.com> References: <20200922101225.183554-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200922_061245_732657_4A1FFCE5 X-CRM114-Status: GOOD ( 15.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Suzuki K Poulose , Alexander Shishkin , linux-kernel@vger.kernel.org, James Clark , Leo Yan , Namhyung Kim , Jiri Olsa , Tan Xiaojun , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Scalable Vector Extension (SVE) is an ARMv8 architecture extension that introduces very long vector operations (up to 2048 bits). The SPE profiling feature can tag SVE instructions with additional properties like predication or the effective vector length. Decode the new operation type bits in the SPE decoder to allow the perf tool to correctly report about SVE instructions. Signed-off-by: Andre Przywara --- .../arm-spe-decoder/arm-spe-pkt-decoder.c | 48 ++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index a033f34846a6..f0c369259554 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -372,8 +372,35 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, } case ARM_SPE_OP_TYPE: switch (idx) { - case 0: return snprintf(buf, buf_len, "%s", payload & 0x1 ? + case 0: { + size_t blen = buf_len; + + if ((payload & 0x89) == 0x08) { + ret = snprintf(buf, buf_len, "SVE"); + buf += ret; + blen -= ret; + if (payload & 0x2) + ret = snprintf(buf, buf_len, " FP"); + else + ret = snprintf(buf, buf_len, " INT"); + buf += ret; + blen -= ret; + if (payload & 0x4) { + ret = snprintf(buf, buf_len, " PRED"); + buf += ret; + blen -= ret; + } + /* Bits [7..4] encode the vector length */ + ret = snprintf(buf, buf_len, " EVLEN%d", + 32 << ((payload >> 4) & 0x7)); + buf += ret; + blen -= ret; + return buf_len - blen; + } + + return snprintf(buf, buf_len, "%s", payload & 0x1 ? "COND-SELECT" : "INSN-OTHER"); + } case 1: { size_t blen = buf_len; @@ -403,6 +430,25 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, ret = snprintf(buf, buf_len, " NV-SYSREG"); buf += ret; blen -= ret; + } else if ((payload & 0x0a) == 0x08) { + ret = snprintf(buf, buf_len, " SVE"); + buf += ret; + blen -= ret; + if (payload & 0x4) { + ret = snprintf(buf, buf_len, " PRED"); + buf += ret; + blen -= ret; + } + if (payload & 0x80) { + ret = snprintf(buf, buf_len, " SG"); + buf += ret; + blen -= ret; + } + /* Bits [7..4] encode the vector length */ + ret = snprintf(buf, buf_len, " EVLEN%d", + 32 << ((payload >> 4) & 0x7)); + buf += ret; + blen -= ret; } else if (payload & 0x4) { ret = snprintf(buf, buf_len, " SIMD-FP"); buf += ret; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel