From: Gavin Shan <gshan@redhat.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, anshuman.khandual@arm.com,
robin.murphy@arm.com, linux-kernel@vger.kernel.org,
shan.gavin@gmail.com, catalin.marinas@arm.com, will@kernel.org
Subject: [PATCH v2 0/2] arm64/mm: Enable color zero pages
Date: Wed, 23 Sep 2020 15:37:19 +1000 [thread overview]
Message-ID: <20200923053721.28873-1-gshan@redhat.com> (raw)
The feature of color zero pages isn't enabled on arm64, meaning all
read-only (anonymous) VM areas are backed up by same zero page. It
leads pressure to L1 (data) cache on reading data from them. This
tries to enable color zero pages.
PATCH[1/2] decouples the zero PGD table from zero page
PATCH[2/2] allocates the needed zero pages according to L1 cache size
Changelog
=========
v2:
* Rebased to 5.9.rc6 (Gavin)
* Retrieve cache topology from ACPI/DT (Will/Robin)
Gavin Shan (2):
arm64/mm: Introduce zero PGD table
arm64/mm: Enable color zero pages
arch/arm64/include/asm/cache.h | 3 ++
arch/arm64/include/asm/mmu_context.h | 6 +--
arch/arm64/include/asm/pgtable.h | 11 ++++-
arch/arm64/kernel/cacheinfo.c | 67 ++++++++++++++++++++++++++++
arch/arm64/kernel/setup.c | 2 +-
arch/arm64/kernel/vmlinux.lds.S | 4 ++
arch/arm64/mm/init.c | 37 +++++++++++++++
arch/arm64/mm/mmu.c | 7 ---
arch/arm64/mm/proc.S | 2 +-
drivers/base/cacheinfo.c | 3 +-
include/linux/cacheinfo.h | 6 +++
11 files changed, 132 insertions(+), 16 deletions(-)
--
2.23.0
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next reply other threads:[~2020-09-23 5:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-23 5:37 Gavin Shan [this message]
2020-09-23 5:37 ` [PATCH v2 1/2] arm64/mm: Introduce zero PGD table Gavin Shan
2020-09-23 5:37 ` [PATCH v2 2/2] arm64/mm: Enable color zero pages Gavin Shan
2020-09-23 8:43 ` [PATCH v2 0/2] " Catalin Marinas
2020-09-23 22:47 ` Gavin Shan
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