From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F01EC2D0A8 for ; Wed, 23 Sep 2020 20:39:08 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F04D920725 for ; Wed, 23 Sep 2020 20:39:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="I0tUEw1a" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F04D920725 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UYiQ5km+aTV1O6HYdH43f2CVclxZJFu5gCm3TmeaavM=; b=I0tUEw1akbATLCHBv6mmmNOMM GDvoCF127o/4AzTqm8ZJ8v27nN4u+ZdCw3HZdc7F9o5hRA6b61mL/CMfkqhJRll786pckyj9Vgo55 33ASrlqPL2jud2S9XXCwnmjlkuBlA90rUn1SvWen9KlDLT8JDVaAJlroC9ymhqsgVyndJXYNtsec4 +Bty7c3UrZN10imjInTbOsr3GRm77scPj5apOpqFR96K0AmuV9+Zu6W0SFHHAQjhJzPGCgUE7y3ih xkEmEbMV49JmNSO22q2S++MKPTtSRYD56wACbdeO9zVnimFn0BV1RCA0LCCFtXn+rsq4ZwwUD9rhG uS/HZPcHA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLBWG-0006Vl-QX; Wed, 23 Sep 2020 20:37:40 +0000 Received: from mail-io1-f66.google.com ([209.85.166.66]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLBWD-0006Uz-TN for linux-arm-kernel@lists.infradead.org; Wed, 23 Sep 2020 20:37:38 +0000 Received: by mail-io1-f66.google.com with SMTP id y13so955530iow.4 for ; Wed, 23 Sep 2020 13:37:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=zyDlLJKi1LCBEhn98FTUiRp7YabuHkI2jkXtBu/lK3s=; b=fUqEZaM9sEEfA1+bW/lWmM0f8ICoKMtpoHE/59kMvHkw6SdiSoZy44zWRCqtU7qLSL CjSHHoDG0J5WrX4u8+TmTYoa8E9NLb9jar4NAgU4l1vMR0wGaKU/qQz+u/m3DOuDN9hI kHeh+MoARo+VjzI6/pBMNGAYLTMj/hJVbqTMzING/2sodYI+BtfSauGSE2D3kKuvyW7m Z5eEkirsaO2DdnZbwiy8pq0e8enQiXO7Ds6E4fZuSv1xlJXcNuHRMKlYc6qP4fBE235S 1KD2lPoujnRdfNlL8j9givm2yOzk733xpf21t/76p6xoDak4+DqeYxrJE/ubuRIPWMaJ 1sUg== X-Gm-Message-State: AOAM533Rif1pF5Et/iIBJwrRPSsX3jyEX62+e2dYJuC4W/g0Rkf0OKLK PitiGm36qa5/1PWvSkPGorMpN+9dkuQK2Nc= X-Google-Smtp-Source: ABdhPJzOk91DVHwMgV1G87qFRX0v0A4pJbMZa2BM4Q3CybLgZllhTEogwEBHo28xHFn87yVHkglBUg== X-Received: by 2002:a05:6638:250d:: with SMTP id v13mr1002429jat.50.1600893457259; Wed, 23 Sep 2020 13:37:37 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id k16sm383922ilc.38.2020.09.23.13.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 13:37:36 -0700 (PDT) Received: (nullmailer pid 1262913 invoked by uid 1000); Wed, 23 Sep 2020 20:37:35 -0000 Date: Wed, 23 Sep 2020 14:37:35 -0600 From: Rob Herring To: Nobuhiro Iwamatsu Subject: Re: [PATCH 1/2] dt-bindings: pwm: Add bindings for Toshiba Visconti PWM Controller Message-ID: <20200923203735.GA1257022@bogus> References: <20200917223140.227542-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20200917223140.227542-2-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200917223140.227542-2-nobuhiro1.iwamatsu@toshiba.co.jp> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200923_163737_948382_82042846 X-CRM114-Status: GOOD ( 20.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, punit1.agrawal@toshiba.co.jp, linux-pwm@vger.kernel.org, Lee Jones , Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 18, 2020 at 07:31:39AM +0900, Nobuhiro Iwamatsu wrote: > Add bindings for the Toshiba Visconti PWM Controller. > > Signed-off-by: Nobuhiro Iwamatsu > --- > .../bindings/pwm/toshiba,pwm-visconti.yaml | 48 +++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/toshiba,pwm-visconti.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/toshiba,pwm-visconti.yaml b/Documentation/devicetree/bindings/pwm/toshiba,pwm-visconti.yaml > new file mode 100644 > index 000000000000..9145e9478b41 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/toshiba,pwm-visconti.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: GPL-2.0 Dual license new bindings please. (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/toshiba,pwm-visconti.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Toshiba Visconti PWM Controller > + > +maintainers: > + - Nobuhiro Iwamatsu > + > +properties: > + compatible: > + items: > + - enum: > + - toshiba,pwm-tmpv7708 The normal order is: vendor,soc-block > + - const: toshiba,pwm-visconti Do you expect a lot of chips with the exact same version of the IP? If not drop. Future chips can always use toshiba,pwm-tmpv7708 as a fallback. > + > + reg: > + # base address and length of the registers block for the PWM. Drop. No need to describe common properties. > + maxItems: 1 > + > + '#pwm-cells': > + # should be 2. See pwm.yaml in this directory for a description of > + # the cells format. Drop. > + const: 2 > + > +required: > + - compatible > + - reg > + - '#pwm-cells' > + > +additionalProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pwm: pwm@241c0000 { > + compatible = "toshiba,pwm-tmpv7708", "toshiba,pwm-visconti"; > + reg = <0 0x241c0000 0 0x1000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pwm_mux>; > + #pwm-cells = <2>; > + }; > + }; > -- > 2.27.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel