From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FF02C4363D for ; Thu, 24 Sep 2020 16:54:19 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A929621D20 for ; Thu, 24 Sep 2020 16:54:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="do3plnNc" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A929621D20 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=AyzH/l9d4we8Pf7yfcn2yUpexk3vfnCYZjVSyLQzuL8=; b=do3plnNc5EKoJ6lQOxEuSN502 z3womaxcFRzPaivnLH9Y80ET6df0k0CZD1Z6DiVo8uZwBQr20AVP9Tvod1DVH+yQ5cIq+UjlNrdWY uDF15F5I5Eona9HET8E9PiTLQ1tB02c8bWU87tOUutplGLOvafxM+qL4n/NzEpwWvLIOlpLFTaVoo +9Njk/kJHLMeW4tSNwdCuGt5WJPo7pVWDKCJKMpx2TvU5KrQGnzS74R2LIbU7x/psdYchalBgGLVE KJ1tmPrSxFOjBGTzqGdi+OC8ft4r+W4rVE/eE6zcH/jjelFzMAuOJlNsH5q7nA/Fn5ol7K4oTJREa xy5DmbAEQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLUUN-00072D-Md; Thu, 24 Sep 2020 16:52:59 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLUUL-00071Y-1o for linux-arm-kernel@lists.infradead.org; Thu, 24 Sep 2020 16:52:58 +0000 Received: from gaia (unknown [31.124.44.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id ACECF21D20; Thu, 24 Sep 2020 16:52:53 +0000 (UTC) Date: Thu, 24 Sep 2020 17:52:51 +0100 From: Catalin Marinas To: Rob Herring Subject: Re: [PATCH v6 2/2] arm64: Add workaround for Arm Cortex-A77 erratum 1508412 Message-ID: <20200924165250.GE28591@gaia> References: <20200924134853.2696503-1-robh@kernel.org> <20200924134853.2696503-2-robh@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200924134853.2696503-2-robh@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200924_125257_196752_F47DF642 X-CRM114-Status: GOOD ( 16.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , Marc Zyngier , James Morse , linux-arm-kernel@lists.infradead.org, Will Deacon , kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 24, 2020 at 07:48:53AM -0600, Rob Herring wrote: > On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load > and a store exclusive or PAR_EL1 read can cause a deadlock. > > The workaround requires a DMB SY before and after a PAR_EL1 register > read. In addition, it's possible an interrupt (doing a device read) or > KVM guest exit could be taken between the DMB and PAR read, so we > also need a DMB before returning from interrupt and before returning to > a guest. > > A deadlock is still possible with the workaround as KVM guests must also > have the workaround. IOW, a malicious guest can deadlock an affected > systems. > > This workaround also depends on a firmware counterpart to enable the h/w > to insert DMB SY after load and store exclusive instructions. See the > errata document SDEN-1152370 v10 [1] for more information. > > [1] https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf > > Cc: Catalin Marinas > Cc: James Morse > Cc: Suzuki K Poulose > Cc: Will Deacon > Cc: Marc Zyngier > Cc: Julien Thierry > Cc: kvmarm@lists.cs.columbia.edu > Signed-off-by: Rob Herring Reviewed-by: Catalin Marinas I'll leave these patches to Will for 5.10. Thanks. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel