From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA369C4727C for ; Fri, 25 Sep 2020 11:36:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 348EA2075E for ; Fri, 25 Sep 2020 11:36:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="BALNhjrI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 348EA2075E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fIHcQrAOFGbQjqD8GZXGEla1jOzl0Smwqv8fN+U3JYI=; b=BALNhjrIpPT5dJTrV9V1K8O0C 2MaI9AiNpMb5TMejJnd2B8NzFld0wM2iUDLtEecug5UxxiYztx7GDduwaJTKGGHwxcIbvflQFda23 PuYyrDyIxosLcyk+r5CxVC/3LJU8BBCD27f9qEmlqf6+EdDzke1V5Q3JltBU83gu4qLJaDjb9w3Gj KFRF2ZU6iohN5upW5v3s+d9KK75FfXsTewrULebqQ2OcRqW/00ROZXffgejxP8e7zVmVn7BzVPwJ5 d5yivIiavmfVBiIe1vnaI6JjP0XBVS39FG1+wtc4hrj6G7buDw9XG+4UaSxMFjghM3qiJHSiQjA4a iHDWfjsNQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLlzy-0005R1-Mr; Fri, 25 Sep 2020 11:34:46 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLlzr-0005Ow-Ee for linux-arm-kernel@lists.infradead.org; Fri, 25 Sep 2020 11:34:43 +0000 Received: from gaia (unknown [31.124.44.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 358C421741; Fri, 25 Sep 2020 11:34:36 +0000 (UTC) Date: Fri, 25 Sep 2020 12:34:33 +0100 From: Catalin Marinas To: Andrey Konovalov Subject: Re: [PATCH v3 29/39] arm64: mte: Switch GCR_EL1 in kernel entry and exit Message-ID: <20200925113433.GF4846@gaia> References: <4e503a54297cf46ea1261f43aa325c598d9bd73e.1600987622.git.andreyknvl@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4e503a54297cf46ea1261f43aa325c598d9bd73e.1600987622.git.andreyknvl@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200925_073439_673389_5CE0B4CB X-CRM114-Status: GOOD ( 22.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Marco Elver , Elena Petrova , Kevin Brodsky , Will Deacon , Branislav Rankov , kasan-dev@googlegroups.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexander Potapenko , Evgenii Stepanov , Andrey Ryabinin , Andrew Morton , Vincenzo Frascino , Dmitry Vyukov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 25, 2020 at 12:50:36AM +0200, Andrey Konovalov wrote: > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > index ff34461524d4..c7cc1fdfbd1a 100644 > --- a/arch/arm64/kernel/entry.S > +++ b/arch/arm64/kernel/entry.S > @@ -175,6 +175,49 @@ alternative_else_nop_endif > #endif > .endm > > + .macro mte_set_gcr, tmp, tmp2 > +#ifdef CONFIG_ARM64_MTE > +alternative_if_not ARM64_MTE > + b 1f > +alternative_else_nop_endif You don't need the alternative here. The macro is only invoked in an alternative path already (I'd be surprised if it even works, we don't handle nested alternatives well). > + /* > + * Calculate and set the exclude mask preserving > + * the RRND (bit[16]) setting. > + */ > + mrs_s \tmp2, SYS_GCR_EL1 > + bfi \tmp2, \tmp, #0, #16 > + msr_s SYS_GCR_EL1, \tmp2 > + isb > +1: > +#endif > + .endm > + > + .macro mte_set_kernel_gcr, tsk, tmp, tmp2 What's the point of a 'tsk' argument here? > +#ifdef CONFIG_KASAN_HW_TAGS > +#ifdef CONFIG_ARM64_MTE Does KASAN_HW_TAGS depend on ARM64_MTE already? Just to avoid too may ifdefs. Otherwise, you can always write it as: #if defined(CONFIG_KASAN_HW_TAGS) && defined(CONFIG_ARM64_MTE) to save two lines (and its easier to read). > +alternative_if_not ARM64_MTE > + b 1f > +alternative_else_nop_endif > + ldr_l \tmp, gcr_kernel_excl > + > + mte_set_gcr \tmp, \tmp2 > +1: > +#endif > +#endif > + .endm > + > + .macro mte_set_user_gcr, tsk, tmp, tmp2 > +#ifdef CONFIG_ARM64_MTE > +alternative_if_not ARM64_MTE > + b 1f > +alternative_else_nop_endif > + ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER] > + > + mte_set_gcr \tmp, \tmp2 > +1: > +#endif > + .endm > + > .macro kernel_entry, el, regsize = 64 > .if \regsize == 32 > mov w0, w0 // zero upper 32 bits of x0 > @@ -214,6 +257,8 @@ alternative_else_nop_endif > > ptrauth_keys_install_kernel tsk, x20, x22, x23 > > + mte_set_kernel_gcr tsk, x22, x23 > + > scs_load tsk, x20 > .else > add x21, sp, #S_FRAME_SIZE > @@ -332,6 +377,8 @@ alternative_else_nop_endif > /* No kernel C function calls after this as user keys are set. */ > ptrauth_keys_install_user tsk, x0, x1, x2 > > + mte_set_user_gcr tsk, x0, x1 > + > apply_ssbd 0, x0, x1 > .endif > > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > index 393d0c794be4..c3b4f056fc54 100644 > --- a/arch/arm64/kernel/mte.c > +++ b/arch/arm64/kernel/mte.c > @@ -22,6 +22,8 @@ > #include > #include > > +u64 gcr_kernel_excl __ro_after_init; > + > static void mte_sync_page_tags(struct page *page, pte_t *ptep, bool check_swap) > { > pte_t old_pte = READ_ONCE(*ptep); > @@ -116,6 +118,13 @@ void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag) > return ptr; > } > > +void mte_init_tags(u64 max_tag) > +{ > + u64 incl = GENMASK(max_tag & MTE_TAG_MAX, 0); > + > + gcr_kernel_excl = ~incl & SYS_GCR_EL1_EXCL_MASK; > +} > + > static void update_sctlr_el1_tcf0(u64 tcf0) > { > /* ISB required for the kernel uaccess routines */ > @@ -151,7 +160,11 @@ static void update_gcr_el1_excl(u64 excl) > static void set_gcr_el1_excl(u64 excl) > { > current->thread.gcr_user_excl = excl; > - update_gcr_el1_excl(excl); > + > + /* > + * SYS_GCR_EL1 will be set to current->thread.gcr_user_incl value ^^^^^^^^^^^^^ That's gcr_user_excl now. > + * by mte_restore_gcr() in kernel_exit, I don't think mte_restore_gcr is still around in this patch. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel